Cognitive Radio Technology

In this work, we discuss techniques for coherently detecting turbo coded orthogonal frequency division multiplexed (OFDM) signals, transmitted through frequency selective Rayleigh (the magnitude of each channel tap is Rayleigh distributed) fading channels having a uniform power delay profile. The channel output is further distorted by a carrier frequency and phase offset, besides additive white Gaussian noise. A new frame structure for OFDM, consisting of a known preamble, cyclic prefix, data and known postamble is proposed, which has a higher throughput compared to the earlier work. A robust turbo decoder is proposed, which functions effectively over a wide range of signal-to-noise ratio (SNR). Simulation results show that it is possible to achieve a bit-error-rate (BER) of $$10^{-5}$$10-5 at an SNR per bit as low as 8 dB and throughput of 82.84 %, using a single transmit and two receive antennas. We also demonstrate that the practical coherent receiver requires just about 1 dB more power compared to that of an ideal coherent receiver, to attain a BER of $$10^{-5}$$10-5. The key contribution to the good performance of the practical coherent receiver is due to the use of a long preamble (512 QPSK symbols), which is perhaps not specified in any of the current wireless communication standards. We have also shown from computer simulations that, it is possible to obtain even better BER performance, using a better code. A simple and approximate Cramer---Rao bound on the variance of the frequency offset estimation error for coherent detection, is derived. The proposed algorithms are well suited for implementation on a DSP-platform.

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Coherent Detection of Turbo-Coded OFDM Signals Transmitted Through Frequency Selective Rayleigh Fading Channels with Receiver Diversity and Increased Throughput

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. This paper presents a novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems. The proposed design employs a low-cost computation scheme to enable 1536-point FFT, which significantly reduces hardware costs as well as power consumption. In conjunction with the aforementioned 1536-point FFT computation scheme, the proposed design included an efficient three-stage SDF pipeline architecture on which to implement a radix-3 FFT. The new radix-3 SDF pipeline FFT processor simplifies its data flow and is easy to control, and the complexity of the resulting hardware is lower than that of existing structures. This paper also formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme. The proposed design was implemented using 90 nm CMOS technology. Postlayout simulation results revealed a die area of approximately $1.44 \times 1.44~\mathrm{mm}^{2}$ with power consumption of only 9.3 mW at 40 MHz.

Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems

In an orthogonal frequency division multiplexing (OFDM)-based digital transmitter, the inverse fast Fourier transform (IFFT) processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the Cooley–Tukey-based decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed ‘pass-logic’. These replacements can be possible because the inputs are bitwise with binary-phase shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for 8 to 128 points (N) were implemented with multipliers and ‘pass-logics’. The performance improvements (PIs) of the proposed FFT/IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the total power by 6.5%. The same implementation on an ASIC, consumed 28% less power and 27% lesser gates. In 128-point implementation, these PIs are more than those of the 64-point, thus PI is in upward trend as N increases. A chip for FFT processing as per IEEE 802.11a specifications (64-point, 16-bit data) is designed with pass-logics, which uses 24 947 gates and consumes 6.45 mW at 1.8 V, 20 MHz in 0.18 µm 1P6M CMOS process.

Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

In modem communications the FFT/IFFT has been normally used in recent years due to its effectiveness in OFDM applications. In this paper multiplierless radix-2/4 FFT architecture using MBSLS was proposed, but here constant multiplication is replaced by shift and add structure unit. The memory of the twiddle factor is minimized by increasing the computation speed with the help of Winograd Fourier transform algorithm. Thus the proposed method offers minimal hardware requirement as well as reduction in complex multiplication in FFT calculation. This method achieves good performance in terms of less area. This architecture has been simulated in Xilinx ISE12.14 software by using Verilog coding and is used in the mobile Wi-MAX application in OFDM.

Radix-2/4 FFT Multiplierless Architecture Using MBSLS in OFDM Applications

4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications

This paper proposes a three-stage rearrangeable polygonal switching network (PSN) for interconnecting one-sided input-output terminals. In comparing our PSN with a three-stage one-sided Clos switching network of the same size and with the same number of switches, we prove that rearrangeability of a PSN is better than that of a Clos switching network. Also, the switching efficiency of the PSN is explored.

A three-stage one-sided rearrangeable polygonal switching network

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.

Design of a low power viterbi decoder for wireless communication applications

Orthogonal Frequency-Division Multiplexing (OFDM) systems can efficiently combat the issue of frequency-selective fading channels. Therefore, OFDM has become one of the most popular baseband modulation techniques for wireless communications. This paper presents the design and implementation of a low-power OFDM baseband receiver for wireless local area networks (WLAN). The proposed architecture employs low-power register files and resource-sharing techniques, thus consuming less power than many existing works. The proposed design adopts a number of area-efficient hardware structures to further reduce the hardware cost. Finally, because it is designed using 0.18 μm CMOS technology, the core of the proposed chip has approximately 239K gates, and its power consumption is approximately 36 mW at 20 MHz.

Mao-Hsu Yen

Papers

A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications

A three-stage one-sided rearrangeable polygonal switching network

Design of a low power viterbi decoder for wireless communication applications

Design and implementation of a low-power OFDM receiver for wireless communications

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