M
Marcelo A. C. Fernandes
Researcher at Federal University of Rio Grande do Norte
Publications - 97
Citations - 636
Marcelo A. C. Fernandes is an academic researcher from Federal University of Rio Grande do Norte. The author has contributed to research in topics: Field-programmable gate array & Computer science. The author has an hindex of 12, co-authored 85 publications receiving 419 citations. Previous affiliations of Marcelo A. C. Fernandes include University of Rio Grande & State University of Campinas.
Papers
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Journal ArticleDOI
Parallel Implementation of Reinforcement Learning Q-Learning Technique for FPGA
TL;DR: A parallel fixed-point Q-learning algorithm architecture implemented on field programmable gate arrays (FPGA) focusing on optimizing the system processing time is proposed.
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A Survey and Taxonomy of FPGA-based Deep Learning Accelerators
Ahmed Ghazi Blaiech,Ahmed Ghazi Blaiech,Khaled Ben Khalifa,Khaled Ben Khalifa,Carlos Valderrama,Marcelo A. C. Fernandes,Mohamed Hedi Bedoui +6 more
TL;DR: This paper briefly review recent work related to the implementation of deep learning algorithms in FPGAs, and analyzes and compares the design requirements and features of existing topologies to finally propose development strategies and implementation architectures for better use of FPGA-based deep learning topologies.
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Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA
TL;DR: This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained with a least mean square (LMS) algorithm.
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Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
TL;DR: A neural network hardware implementation developed on a field-programmable gate array (FPGA) and supports deep neural network trained with the stacked sparse autoencoder (SSAE) technique, enabling deep learning techniques to be applied for problems with large data amounts.
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High-Performance Parallel Implementation of Genetic Algorithm on FPGA
TL;DR: In this paper, the authors proposed a full-parallel implementation of a GA algorithm on a field-programmable gate array (FPGA) to optimize the system's processing time and area occupancy.