A review of lead-free solders for electronics applications

Aerosol Jet Printing (AJP) is an emerging contactless direct write approach aimed at the production of fine features on a wide range of substrates. Originally developed for the manufacture of electronic circuitry, the technology has been explored for a range of applications, including, active and passive electronic components, actuators, sensors, as well as a variety of selective chemical and biological responses. Freeform deposition, coupled with a relatively large stand-off distance, is enabling researchers to produce devices with increased geometric complexity compared to conventional manufacturing or more commonly used direct write approaches. Wide material compatibility, high resolution and independence of orientation have provided novelty in a number of applications when AJP is conducted as a digitally driven approach for integrated manufacture. This overview of the technology will summarise the underlying principles of AJP, review applications of the technology and discuss the hurdles to more widespread industry adoption. Finally, this paper will hypothesise where gains may be realised through this assistive manufacturing process.

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A review of aerosol jet printing—a non-traditional hybrid process for micro-manufacturing

I und J

After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies [2015-0158]

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

The objectives of this paper in the context of aerosol jet printing (AJP)—an additive manufacturing (AM) process—are to: (1) realize in situ online monitoring of print quality in terms of line/electronic trace morphology; and (2) explain the causal aerodynamic interactions that govern line morphology based on a two-dimensional computational fluid dynamics (2D-CFD) model. To realize these objectives, an Optomec AJ-300 aerosol jet printer was instrumented with a charge coupled device (CCD) camera mounted coaxial to the nozzle (perpendicular to the platen). Experiments were conducted by varying two process parameters, namely, sheath gas flow rate (ShGFR) and carrier gas flow rate (CGFR). The morphology of the deposited lines was captured from the online CCD images. Subsequently, using a novel digital image processing method proposed in this study, six line morphology attributes were quantified. The quantified line morphology attributes are: (1) line width, (2) line density, (3) line edge quality/smoothness, (4) overspray (OS), (5) line discontinuity, and (6) internal connectivity. The experimentally observed line morphology trends as a function of ShGFR and CGFR were verified with computational fluid dynamics (CFD) simulations. The image-based line morphology quantifiers proposed in this work can be used for online detection of incipient process drifts, while the CFD model is valuable to ascertain the appropriate corrective action to bring the process back in control in case of a drift. [DOI: 10.1115/1.4034591]

Computational Fluid Dynamics Modeling and Online Monitoring of Aerosol Jet Printing Process

The current feed capability of typical flip chip electrical interconnects is constrained by the solder alloy, as it is more susceptible to electromigration than the copper used for the pads and wires. Hence, interconnects formed by copper only mitigate the electromigration risk and/or allow to increase the current limit of the all-copper interconnect. In this work, two methods to form all-copper flip chip interconnects at an annealing temperature of 250 °C are presented. The interconnects in the contact region between Cu pillars and Cu pads with a pitch down to 150 µm are formed by Cu nanoparticle self-assembly and sintering. In the first method, the entire gap between a Cu pillar chip and a substrate was filled with a Cu nano-suspension. The formation of capillary bridges during the evaporation of the dispersant directed the self-assembly of the nanoparticles towards the contact region between Cu pillars and Cu pad. In the second method, the Cu pillar chip was dipped into a film of the Cu nano-suspension, followed by a transfer, placement and release with a die bonder onto pads on a substrate. The annealing of the Cu nanoparticles is performed in both cases in a reducing formic acid atmosphere. The first method was more susceptible to the formation of shorts between pillars, whereas the second method resulted in electrical functional chip to substrate assemblies. Interconnects with a mean electrical resistance of 26 ± 3 mΩ and a shear strength ranging from 4.6 to 12.3 MPa were achieved. The sintered Cu nanoparticles bridged gaps up to 10 µm between copper pillars and pads, demonstrating the potential to apply the joint also on non-planar substrates. Nevertheless, imperfections such as voids and cracks are still present in the joints and need further process development, to improve the quality and process robustness further.

Nanoparticle assembly and sintering towards all-copper flip chip interconnects

In this study we successfully bonded silicon wafer substrates with metal based thermocompression technology. This technology has the advantage of inherent possibility of hermetic sealing and electrical contact. We used three different kinds of metals: gold, copper and aluminum. We will show the hermeticity, bonding strength and reliability of the different processes and compare the results.

Investigations of thermocompression bonding with thin metal layers

Aerosol Jet Printing of Nano Particle Based Electrical Chip Interconnects

In this paper, wafer-to-wafer AuSi eutectic bonding was investigated and evaluated with various sets of experimental parameters. Single crystalline Si and amorphous Si were bonded with different dimension Au layers and observed by optical measurements. Material composition, adhesion layer, electrical insulation, bonding parameters, and surface pre-treatments were discussed and have improved bonding performance. Bond strength determined by micro-chevron-test and shear test was evaluated as well as hermeticity. High bond yield was achieved with 4 inch and 6 inch wafer stacks.

Development and evaluation of AuSi eutectic wafer bonding

The low temperature joining of semiconductor substrates on wafer level by solid-liquid inter-diffusion bonding using the Cu/Ga and Au/In systems is investigated regarding the bonding parameters and their influence on bond interface properties. The focus is on temperature dependence and composition of interface. In the case of Cu/Ga bonding, a phase transition from CuGa2 to Cu9Ga4 was found to be primarily responsible for an increase in bonding strength. After the temperature treatment of 90°C, a shear strength of up to 90 MPa could be achieved. Furthermore, the combination of Au and In with composition ratios suitable for AuIn2 and AuIn intermetallic phase formation was investigated. In the case of AuIn shear strength, 96 MPa was achieved using a bonding temperature of 200°C. [2014-0325]

Mario Baum

Papers

Nanoparticle assembly and sintering towards all-copper flip chip interconnects

Investigations of thermocompression bonding with thin metal layers

Aerosol Jet Printing of Nano Particle Based Electrical Chip Interconnects

Development and evaluation of AuSi eutectic wafer bonding

Low-Temperature Wafer Bonding Using Solid-Liquid Inter-Diffusion Mechanism