A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Phase shifting circuit manufacture method and apparatus

A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.

Design rule checking system and method

A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input (205), and a particular set of OPC correction criteria as a second input (260). The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria (210, 240). After the areas on the mask which need correction have been identified (310), optical proximity correction data (320) is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure (320) that corresponds to the hierarchical structure of the integrated circuit layout (310). As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.

Data hierarchy layout correction and verification method and apparatus

Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Dissection of printed edges from a fabrication layout for correcting proximity effects

A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.

Visual inspection and verification system

The focus of this work is to provide a methodology to accurately disposition clear field contaminants at the reticle inspection station. A test mask was designed with programmed resist and chrome defects to simulate clear field contamination. Wafers were printed using a variety of O.5Ojim/O.35im IO.25im lithography processes. We determine printability using I-line and DUV resist under different illumination conditions. We demonstrate that aerial image simulation and defect size are the most practical methodologies to disposition semi-transparent defects. We show Aerial image simulation to correlate with printed wafer results for soft defects.Keywords: reticle, photomask, soft defects, inspection, lithography, printability, AIMS, contamination 1. Introduction As the capability of advanced reticle inspection tools increases, a very large number of defects canbe observed on photomasks which were not previously detectable. Many of these defects may be semi-transparent at the inspection wavelength, but opaque in the photolithography process. Thus, the practiceof dispositioning photomasks based upon opaque defect size alone is in question. With sophisticated tools

Clear-field reticle defect disposition for advanced sub-half-micron lithography

Progressive mask defect problems such as crystal growth or haze are key yield limiters at DUV lithography, especially in 300mm fabs. With the high energy photons involved in DUV lithography and large wafer size requiring longer continuous exposure of masks, chances of photochemical reaction increases significantly on the masks. 
Most of the work published on this subject so far has been focused on defect growth on clear area (on the pattern surface) and on the back-glass of the mask. But there is a new generation of growing defects: crystals that grow on the half-tone (MoSi) film or on the chrome film, on the pattern side of the mask. It is believed that the formation mechanisms and rates are different for these new types of crystals. In light of this instability of masks in volume production, it becomes more important to understand the nature of such defects. The purpose of this investigation is to characterize the nature of these new defect growths and to understand the possible formation mechanisms involved in such problems.

An investigation of a new generation of progressive mask defects on the pattern side of advanced photomasks

DUV lithography has introduced a progressive mask defect growth problem widely known as crystal growth or haze. Even if the incoming mask quality is good, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught in advance during production in the fabs. The ideal reticle quality' control goal should be to detect any nascent progressive defects before they become yield limiting. So, a high-resolution mask inspection is absolutely needed, but the big question is: "how often do fabs need to re-inspect their masks"? Previous work towards finding a cost effective mask re-qualification frequency (V. Samek et al., September 8-10, 1999), was done prior to the above mentioned progressive defect problem that industry started to see at a much higher rate during just the last few years. Other related recent work was done 2004 BACUS conference which is dedicated to DRAM fab data (K. Bhattacharyya et al., 2004). In this paper a realistic mask re-qualification frequency model has been developed based on a large volume of data from an advanced logic fab. This work will compliment previous work in this area done with the data from a DRAM fab (K. Bhattacharyya et al., 2004). Statistical methods are used to analyze mask inspection and product data, which are combined in a stochastic model

A reticle quality management strategy in wafer fabs addressing progressive mask defect growth problem at low k1 lithography

As our chip producing industry rapidly ramps to mass production of the 130nm device technology node and wrapping up the final stages of 90nm node process technology development, the ability to inspect all types of 130nm node masks and early identification of shortcomings in 90nm node mask inspection are extremely important.
In this paper, we share our experience of mask inspection for the 90nm and 130nm nodes, using the advanced TeraStar mask inspection system (KLA-Tencor) with the SEMI programmed defect standard masks, comprising three substrate types (binary, 248nm-KrF MoSi and 193nm-ArF MoSiON). Both Die-to-Die (D2D) and Die-to-Database (DDB) inspections were carried out and the results are presented with our assessments of benefits and shortcomings of those methods. To verify the resulting defects actually impact device functionality, we also carried out systematic printability experiments with our proprietary 130nm and 90nm nodes lithography processes. The wafer results were then compared with mask inspection results and mask measurement data to draw our final conclusions. In addition, we will also present inspection performance of the TeraStar system on our 130nm production masks and very challenging 90nm node (ArF EAPSM/AAPSM) development masks.

Mask Inspection Challenges for 90 nm and 130 nm Device Technology Nodes: Inspection Sensitivity and Printability Study using SEMI Standard Programmed Defect Masks

Silicon Technology Development for the ITRS 65nm-node is in the final stage of an intense 2-year cycle with the full-entitlement technology qualification by the end of 2005. Accordingly, reticle technology development in support of the 65nm-node has advanced a great deal since the initial efforts began several years ago. One of the most challenging aspects of 65nm-node mask technology development is the mask inspection, which is also the main cost-driver for the 65nm-node reticle technology. As a result, controlling 65nm-node reticle cost via leveraging advanced mask inspection technologies has become a leading factor in enabling prolonged success of the 65-nm node technology for years to come. With this paper, we report our closing work on reticle inspection capability development for the 65nm-node process technology development cycle for a full-volume production ramp.

Mark D. Eickhoff

Papers

Clear-field reticle defect disposition for advanced sub-half-micron lithography

An investigation of a new generation of progressive mask defects on the pattern side of advanced photomasks

A reticle quality management strategy in wafer fabs addressing progressive mask defect growth problem at low k1 lithography

Mask Inspection Challenges for 90 nm and 130 nm Device Technology Nodes: Inspection Sensitivity and Printability Study using SEMI Standard Programmed Defect Masks

Advanced reticle inspection challenges and solutions for 65nm node