Two major trends in the digital design industry are the increase insystem complexity and the increasing importance of short designtimes. The rise in design complexity is motivated by consumerdemand for higher performance products as well as increases inintegration density which allow more functionality to be placed ona single chip. A consequence of this rise in complexity is a significantincrease in the amount of simulation required to design digitalsystems. Simulation time typically scales as the square of theincrease in system complexity [4]. Short design times are importantbecause once a design has been conceived there is a limited timewindow in which to bring the system to market while its performanceis competitive.Simulation serves many purposes during the design cycle of a digitalsystem. In the early stages of design, high-level simulation isused for performance prediction and analysis. In the middle of thedesign cycle, simulation is used to develop the software algorithmsand refine the hardware. In the later stages of design, simulation isused make sure performance targets are reached and to verify thecorrectness of the hardware and software. The different simulationobjectives require varying levels of modeling detail. To keep designtime to a minimum, it is critical to structure the simulation environmentto make it possible to trade-off simulation performance formodel detail in a flexible manner that allows concurrent hardwareand software development.In this paper we describe the different simulation methodologies fordeveloping complex digital systems, and give examples of one suchsimulation environment. The rest of this paper is organized as follows.In Section 2 we describe and classify the various simulationmethodologies that are used in digital system design and describehow they are used in the various stages of the design cycle. In Section3 we provide examples of the methodologies. We describe asophisticated simulation environment used to develop a large ASICfor the Stanford FLASH multiprocessor.

Digital system simulation: methodologies and examples

Two major trends in the VLSI chip design industry are the increase in system complexity and the increasing importance of short design times. The rise in chip complexity is motivated by consumer demand for higher performance products as well as increases in integration density which allow more functionality to be placed on a single chip. A consequence of this rise in complexity is an increasingly apparent chip validation bottleneck. Validation is a simulation intensive task and simulation time scales as the square of the increase in system complexity [9, 7]. Currently, complex VLSI chips take millions of hours of simulation to verify. Short design times are important because once a chip has been conceived there is a limited time window in which to bring the chip to market so that it will have competitive performance. For a new chip or system to be competitive when it reaches the marketplace, its performance must match the performance growth of the rest of the industry. This means that a complex chip that takes too long to design might miss its market window and by the time it reaches the market its performance will be uncompetitive. To reduce design time, system design bottlenecks need to be removed. System emulation and prototyping technology can play an important role in relieving the simulation bottleneck and managing system complexity.

Emulation and Prototyping Of Digital Systems

This paper presents a prototyping environment for evaluation of hardware/software systems in their real world environment. This environment is used as a hardware/software platform for developing and testing systems without having to wait for fabrication of the system. The high-level description of the system is fast compiled into an arrangement of programmable and configurable platforms. This platform is based on a microprocessor-based architecture for software part and a configurable FPGAs based board for hardware part. This paper also treats an application of rapid prototyping for design of robot arm controller.

Rapid prototyping environment for design of hardware/software electronic systems

Time-to-market continues to be The Challenge faced by developers of complex electronic systems. The bottleneck - which was traditionally in the design phase of the project - has now moved downstream to the system-level verification stage. The growing adoption of top-down design methodologies based on HDL and synthesis has made the generation of large multi-million gate designs easier than before. The efficient verification of those newly created gates in the final system is now the key to solving The Challenge. Technologies such as rapid system prototyping, ASIC emulation and formal verification offer the potential to completely verify the full system. Hardware and software co-design and HDL test benches offer the potential to feed real world inputs to the verification process. This panel will assess the outlook for verification for complex systems. We will focus on enabling technologies which show promise in this area, both now and for the future. The panel will present a mixture of tutorial material, leading edge academic work, current technology and the user's perspective. In addition to current and future technologies, each speaker will specifically address how design methodology is impacted by their choice of verification methodology. The discussion of the panel will focus on: -What's required from the EDA industry to make their customers successful in the future? -System level verification can be quite expensive. Is the promised Return-On-Investment really there? -Which technologies are usable without turning design methodologies upside down? -Just what is product and what is research in this area? The target audience includes chip and system designers, design managers and executive management who are pondering the benefits and costs of implementing system-level verification. The panelists represent a mix of academia, companies offering verification solutions and users of system-level verification products. The panel will begin with a tutorial on Formal Verification. All other panelists will be limited to a short position statement, allowing ample time for discussion. Each panelist will provide their own perspective of system-level verification challenges.

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Martin Baynes

Papers

Complex system verification (panel): the challenge ahead