A data transmission system includes probes (probe A, probe B) connected between end user sites (site A, site B) and a data switching network (12). Each probe is connected to the switching network (12) via an access channel (20, 21, 26 or 27) wherein transmission circuits establish paths between the sites through the access channel (20, 21, 26 or 27) and switching network (12). The probes capture and retransmit data traveling between the sites over respective transmission circuits, and can thereby insert service level anaylsis (SLA) messages into data traffic in order to actively communicate network performance information to other probes. For each transmission circuit, the probes periodically collect measurements related to one or more network performance metrics, including round-trip delay (RTD), data delivery ratio (DDR) and network availability. During each SLA measurement cycle, a sequence of SLA messages is exchanged over each transmission circuit, which messages contain data used to determine RTD and DDR.

Method and apparatus for performing service level analysis of communications network performance metrics

An ATM network switch and method of utilization for adaptively providing integrated services therein is disclosed. In providing such integrated services, if the allocated bandwidth for one connection has been consumed, or if the connection is not entitled to allocated bandwidth, the connection can optionally use dynamic bandwidth arbitration, or a combination of both allocated and dynamic. The switch includes an input port processor, a bandwidth arbiter, and an output port processor. Cells are transmitted from the input to the output, under the control of respective port processors and the bandwidth arbiter. Flow control is implemented on a per-connection basis. Individual queues are then assigned to traffic type groups in order to provide traffic type flow control. Based upon prioritization information associated with the cell at the input, cells are prioritized and transmitted from the output, with each cell maintained in the same order, relative to other cells on a connection, in which it was received.

Allocated and dynamic bandwidth management

In a module socket, a connecter and a connector are connected by wiring, and three LED modules are connected in parallel with respect to a constant voltage circuit unit via the wiring. Each module has a constant current circuit unit and an LED mounting unit. The constant current circuit unit includes one resistor and two transistors mounted on a surface of a sub-substrate on which a conductive land is formed. The sub-substrate is bonded to a main substrate.

Multichip led lighting device

A multi-layered information recording medium including a plurality of recording layers, the multi-layered information recording medium comprising: a user data area for recording user data; and a plurality of spare areas including at least one replacement region, wherein when the user data area includes at least one defect region, the at least one replacement region may be used in place of the at least one defect region, wherein a first spare area of the plurality of spare areas is positioned so as to be contiguous to a first user data area of a first recording layer, a second spare area of the plurality of spare areas is positioned so as to be contiguous to a second user data area of a second recording layer, and the first spare area and the second spare area are positioned approximately at the same radial position on the multi-layered information recording medium.

Multi-layered information recording medium, recording apparatus, and recording method

An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).

Asynchronous transfer mode based service consolidation switch

PURPOSE:To obtain the routing network monitor system attended with confirmation of a real passing path of a packet with respect to the routing network monitor system CONSTITUTION:The system is provided with a monitor control section 2 inserting a path check packet and recovering the packet to a routing network 1 and with a path monitor section 3 provided to each path in the routing network 1 and providing passing location information corresponding to the path check packet passing through each path and the monitor control section 2 monitors the actual passing state of the routing network 1 based on passing position information of the path check packet to be recovered Preferably, the monitor control section 2 compares the schedule information of a known path with the passing location information of a recovered packet to monitor the state of the routing network 1 Furthermore, the path monitor section 3 is provided with a comparison section comparing the schedule information of the path added to the path check packet with the passing location information of the path monitor section 3 and outputs an alarm signal to the monitor control section 2 when the coincidence of the comparison is not obtained

Routing network monitor system

PROBLEM TO BE SOLVED: To improve the accuracy of phase selection with respect to burst data. SOLUTION: In this method, an edge is detected by sampling data at a plurality of phase points of burst data in a detection window, and based on the edge detection, a burst synchronization circuit selects a phase with respect to burst data. A phase after a prescribed number such as a phase ϕ3 is selected so as to exclude unstable to parts among selected phases corresponding to a plurality of bits in the edge detection window or a phase with a prescribed number of the same consecutive selected phases is selected or the same phase causing a maximum number of times of the same phases is selected for the selected phase with respect to burst data after the edge detection window.

Phase selection method in burst synchronization circuit

PURPOSE:To obtain a simple circuit constitution without requiring a DC connection circuit by connecting a capacity connecting capacitor to the post stage of a branching part for branching a single clock outputted from a DC clock source into plural clocks. CONSTITUTION:A branching part 2 branches an output signal line from a DC clock source 1 into plural lines and is connected to respective terminal resistors 3 through respective output side capacitors 5. Namely a single clock from the DC clock source 1 is branched into plural clocks and the branched clocks are passed through the capacity connecting capacitors 5, so that DC components are cut out from respective clocks and AC clocks are applied to the resistors 3. Since each terminal resistor 3 does not require the execution of termination by an ECL gate circuit like a convensional method and attains its function by considering only impedance matching, useless power consumption due to the combination of the unnecessary ECL gate circuit and the terminal resistor can be reduced.

Clock distributing circuit

Using a switching signal from a coarse/fine switching and operation mode switching circuit, the width of change of a counter control value during power up is increased, and the width of change is reduced once a steady state is reached. In the steady state, the frequency of updating is limited by a control signal from an update permit control circuit. In the steady state, the frequency band of a current source in an LD driving circuit is reduced in width.

Light output control circuit

PROBLEM TO BE SOLVED: To provide a phase comparator and a PLL circuit which surely enable phase comparison of a high speed reference signal with a comparison signal by using a circuit of a low operation speed. SOLUTION: The phase comparator is provided with two edge trigger type RS flip-flops 11, 12 and a logic operation circuit 13. A data signal as the reference signal and a clock signal which has a 1/n times frequency of the data signal and is used as the comparison signal are input in the flip-flop 11. The data signal as the reference signal and a signal which is obtained by inverting the clock signal and used as the comparison signal are input in the flip-flop 12. The logic operation circuit 13 calculates a logical product or a logical sum of output signals of the flip-flops 11, 12, thereby generating an error signal having a unique pulse width corresponding to a phase difference every rise edge of the data signal. COPYRIGHT: (C)2004,JPO

Masaaki Kawai

Papers

Routing network monitor system

Phase selection method in burst synchronization circuit

Clock distributing circuit

Light output control circuit

Phase comparator and phase-locked loop circuit