A data transmission system includes probes (probe A, probe B) connected between end user sites (site A, site B) and a data switching network (12). Each probe is connected to the switching network (12) via an access channel (20, 21, 26 or 27) wherein transmission circuits establish paths between the sites through the access channel (20, 21, 26 or 27) and switching network (12). The probes capture and retransmit data traveling between the sites over respective transmission circuits, and can thereby insert service level anaylsis (SLA) messages into data traffic in order to actively communicate network performance information to other probes. For each transmission circuit, the probes periodically collect measurements related to one or more network performance metrics, including round-trip delay (RTD), data delivery ratio (DDR) and network availability. During each SLA measurement cycle, a sequence of SLA messages is exchanged over each transmission circuit, which messages contain data used to determine RTD and DDR.

Method and apparatus for performing service level analysis of communications network performance metrics

An ATM network switch and method of utilization for adaptively providing integrated services therein is disclosed. In providing such integrated services, if the allocated bandwidth for one connection has been consumed, or if the connection is not entitled to allocated bandwidth, the connection can optionally use dynamic bandwidth arbitration, or a combination of both allocated and dynamic. The switch includes an input port processor, a bandwidth arbiter, and an output port processor. Cells are transmitted from the input to the output, under the control of respective port processors and the bandwidth arbiter. Flow control is implemented on a per-connection basis. Individual queues are then assigned to traffic type groups in order to provide traffic type flow control. Based upon prioritization information associated with the cell at the input, cells are prioritized and transmitted from the output, with each cell maintained in the same order, relative to other cells on a connection, in which it was received.

Allocated and dynamic bandwidth management

In a module socket, a connecter and a connector are connected by wiring, and three LED modules are connected in parallel with respect to a constant voltage circuit unit via the wiring. Each module has a constant current circuit unit and an LED mounting unit. The constant current circuit unit includes one resistor and two transistors mounted on a surface of a sub-substrate on which a conductive land is formed. The sub-substrate is bonded to a main substrate.

Multichip led lighting device

A multi-layered information recording medium including a plurality of recording layers, the multi-layered information recording medium comprising: a user data area for recording user data; and a plurality of spare areas including at least one replacement region, wherein when the user data area includes at least one defect region, the at least one replacement region may be used in place of the at least one defect region, wherein a first spare area of the plurality of spare areas is positioned so as to be contiguous to a first user data area of a first recording layer, a second spare area of the plurality of spare areas is positioned so as to be contiguous to a second user data area of a second recording layer, and the first spare area and the second spare area are positioned approximately at the same radial position on the multi-layered information recording medium.

Multi-layered information recording medium, recording apparatus, and recording method

An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).

Asynchronous transfer mode based service consolidation switch

PURPOSE: To provide an ATM switch and a path replacing method by the ATM switch capable of making a hardware amount at the time of small scale small and easily increasing switching modules. CONSTITUTION: The plural switching modules 1 arrayed in plural columns and at least one row switch routes corresponding to route information attached to cells so as to transfer inputted information to a target line by a cell unit. More than one path replacing parts 2 are provided between the switching modules in the two mutually adjacent columns among the switching modules in the plural columns and replace the routes between the respective switching modules 1 provided together in the row direction of one of the columns among the switching modules in the two adjacent columns and the respective switching modules 1 provided together in the row direction of the other column among the switching modules in the two adjacent columns.

Atm switch and path replacing method by the atm switch

PURPOSE:To prevent the influence of variation in power supply voltage by simple constitution in respect to an I/O interface circuit consisting of ECL circuits to be driven by single positive power supply voltage. CONSTITUTION:In the I/O interface circuit provided with an output interface part 3 having an output buffer 1 and an output transistor(TR) 2 consisting of an ECL circuit and an input interface part 6 having an input buffer 4 and a reference circuit 5 consisting of an ECL circuit and allowed to be driven by single positive power supply voltage, a band gap reference circuit 7 for impressing stabilized operation voltage VCC to the ground GND is provided to the buffer 1 and the TR 2 of the output interface 3.

Input/output interface circuit

A circuit for generating a discrimination level voltage which is used as a reference voltage to discriminate between two logic levels adjacent to each other in input signals which generally can be in a state corresponding to one of a plurality of different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity of the discrimination level and the frequency at which the levels of the input signals lie in the lower half of the vicinity of the discrimination level are compared, and the discrimination level is controlled so that the above two frequencies are the same.

Masaaki Kawai

Papers

Atm switch and path replacing method by the atm switch

Input/output interface circuit

Circuit for generating discrimination level voltage