A data transmission system includes probes (probe A, probe B) connected between end user sites (site A, site B) and a data switching network (12). Each probe is connected to the switching network (12) via an access channel (20, 21, 26 or 27) wherein transmission circuits establish paths between the sites through the access channel (20, 21, 26 or 27) and switching network (12). The probes capture and retransmit data traveling between the sites over respective transmission circuits, and can thereby insert service level anaylsis (SLA) messages into data traffic in order to actively communicate network performance information to other probes. For each transmission circuit, the probes periodically collect measurements related to one or more network performance metrics, including round-trip delay (RTD), data delivery ratio (DDR) and network availability. During each SLA measurement cycle, a sequence of SLA messages is exchanged over each transmission circuit, which messages contain data used to determine RTD and DDR.

Method and apparatus for performing service level analysis of communications network performance metrics

An ATM network switch and method of utilization for adaptively providing integrated services therein is disclosed. In providing such integrated services, if the allocated bandwidth for one connection has been consumed, or if the connection is not entitled to allocated bandwidth, the connection can optionally use dynamic bandwidth arbitration, or a combination of both allocated and dynamic. The switch includes an input port processor, a bandwidth arbiter, and an output port processor. Cells are transmitted from the input to the output, under the control of respective port processors and the bandwidth arbiter. Flow control is implemented on a per-connection basis. Individual queues are then assigned to traffic type groups in order to provide traffic type flow control. Based upon prioritization information associated with the cell at the input, cells are prioritized and transmitted from the output, with each cell maintained in the same order, relative to other cells on a connection, in which it was received.

Allocated and dynamic bandwidth management

In a module socket, a connecter and a connector are connected by wiring, and three LED modules are connected in parallel with respect to a constant voltage circuit unit via the wiring. Each module has a constant current circuit unit and an LED mounting unit. The constant current circuit unit includes one resistor and two transistors mounted on a surface of a sub-substrate on which a conductive land is formed. The sub-substrate is bonded to a main substrate.

Multichip led lighting device

A multi-layered information recording medium including a plurality of recording layers, the multi-layered information recording medium comprising: a user data area for recording user data; and a plurality of spare areas including at least one replacement region, wherein when the user data area includes at least one defect region, the at least one replacement region may be used in place of the at least one defect region, wherein a first spare area of the plurality of spare areas is positioned so as to be contiguous to a first user data area of a first recording layer, a second spare area of the plurality of spare areas is positioned so as to be contiguous to a second user data area of a second recording layer, and the first spare area and the second spare area are positioned approximately at the same radial position on the multi-layered information recording medium.

Multi-layered information recording medium, recording apparatus, and recording method

An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).

Asynchronous transfer mode based service consolidation switch

PURPOSE:To surely prevent a malfunction with simple configuration with respect to the malfuction preventing circuit for phase locked loop circuit to prevent the phase locked loop circuit from being locked at any frequency excepting for the desired frequency CONSTITUTION:A phase locked loop circuit is provided to frequency divide the output signal of a voltage controlled oscillator (VCO) 1 with a frequency divider 2, to compare the phase with the output signal of a synthesizer 3 by using a phase comparator 4, to pass a phase comparison output signal through low-pass filter 5 and an amplifier 6 and to define it as the control voltage of the VCO 1 Further, a malfunction preventing circuit 9 is provided to get out of an erroneous frequency pullNn state by resetting the control voltage of the VCO 1 at a prescribed value such as an initial value or considerably changing the control voltage in the manner of a pulse when a phase lock state is detected by a lock detection part 7 and R,& a correction judge part 8 judgesNthe lock frequency is wrong

Malfunction preventing circuit for phase locked loop circuit

PROBLEM TO BE SOLVED: To provide a burst synchronous circuit in a receiver between communi cation equipments making burst transmission so as to receive burst data proper ly. SOLUTION: The burst synchronization circuit is used to match a bit phase of burst data BD received by a receiver between communication equipments for burst transmission based on a clock signal CLK. After a means 21 delays the data BD by picture phase amount and plural data are outputted by triggering with the CLK and a means 22 detects one change point with different logic adjacent to plural output data from the means 21. Thus, one side edge is detected and a means 23 is used to obtain an optimum phase entering a safe region at which the CLK points out properly data by adding a prescribed phase to a phase of one side edge. Then data of an optimum phase obtained by the means 23 are selected and outputted among plural output data of the means 21.

Burst synchronous circuit

A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st˜n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

One bit error correction method having actual data reproduction function

PURPOSE: To provide a monitoring system which can insert and extract an intra-device monitoring OAM cell in the same interface part by providing loop back parts between multiplex parts and separation parts for interface parts. CONSTITUTION: When the intra-device monitoring OAM cell C inserted from the interface parts 10 1 -10N and into which prescribed loop back information are written reaches the loop back parts 20 1 -20N provided on a device using the cell for information transmission, the loop back parts 20 1 -20N rewrite loop back information. Then, original loop back information is comparison-collated with rewritten loop back information in an OAM cell C' returned to the interface parts 10 1 -10M, and it is judged whether the operation of the device normally functions or not. Thus, the monitoring system which can insert and extract the intra-device monitoring OAM cell in the same interface part of the device using the cell for information transmission can be realized and a processing can be simplified with such constitution. COPYRIGHT: (C)1993,JPO&Japio

Device monitoring system

A 16-channel multiplexer and demultiplexer LSI chip set has been designed, fabricated, and tested. A maximum operating speed of 3 Gb/s and a low power consumption of 2.0 W were realized. Using these ICs, the required mounting space was reduced by 1/70 and power consumption to 1/5 that of conventional discrete medium-scale integrated circuits. A high transconductance was obtained by using 1- mu m-long tungsten-silicide gate MESFETs. The transconductance was 270 mS/mm for a threshold voltage of -0.20 V at a gate bias of 0.6 V, and 230 mS/mm for a threshold voltage of -0.70 V at a gate bias of 0 V. A 5-20- mu m logic gate width was adopted to obtain wideband operation and lower power consumption. These optimizations were performed by computer simulation using the modified SPICE model. >

Masaaki Kawai

Papers

Malfunction preventing circuit for phase locked loop circuit

Burst synchronous circuit

One bit error correction method having actual data reproduction function

Device monitoring system

3-Gbit/s, 16-channel GaAs multiplexer and demultiplexer LSIs