An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

The introduction of enhancement-mode gallium-nitride-based power devices such as the eGaN FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the printed circuit board (PCB) layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET-based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This paper will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design, providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Understanding the Effect of PCB Layout on Circuit Performance in a High-Frequency Gallium-Nitride-Based Point of Load Converter

A power semiconductor module with its thermal resistance and overall size reduced Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader

Power semiconductor module

The introduction of enhancement mode gallium nitride based power devices such as the eGaN®FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with Silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the PCB layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This work will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter

A power MOS-FET is used as a high side switch transistor for a non-insulated DC/DC converter. An electrode section that serves as a source terminal of the power MOS-FET is connected to one outer lead and two outer leads via bonding wires respectively. The outer lead is an external terminal connected to a path for driving the gate. Each of the outer leads is an external terminal connected to a main current path. Owing to the connection of the main current path and the gate driving path in discrete form, the influence of parasitic inductance can be reduced and voltage conversion efficiency can be improved.

Semiconductor device and power supply system

In a low withstand voltage vertical trench MOSFET having an SJ structure, an N type epitaxial layer which is a current path and a trench structure which extends from a semiconductor surface into the N type epitaxial layer are provided, and a floating P type region is formed in a portion of the N type epitaxial layer positioned below the trench structure. The P type region is formed below the trench structure by ion-implanting P type impurity ions. By forming the P type region below a fine trench gate through ion-implantation, energy for ion-implantation can be reduced, and a fine SJ structure can be fabricated. Accordingly, a device structure which allow formation of a fine SJ structure in a low withstand voltage power MOSFET and a manufacturing method of the same can be provided.

Semiconductor device and manufacturing method of the same, and non-isolated DC/DC converter

A drive circuit for driving a semiconductor element is equipped with: a first switch connected to a positive side of a DC power supply; a second switch connected to the other terminal of the first switch and to a negative side of the DC power supply; a third switch connected to the positive side of the DC power supply; a fourth switch connected to the other terminal of the third switch; a fifth switch connected to the other terminal of the fourth switch and to the negative side of the DC power supply; and a capacitor connected to the other terminal of the first switch and to the other terminal of the fourth switch. A gate of the semiconductor element is connected to the other terminal of said third switch; and a source of the semiconductor element is connected to the negative side of the DC power supply.

Drive circuit and inverter for voltage driving type semiconductor device

A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch disposed between the gate and source of said low-side switch, and a low-side MOSFET 3 for the low-side switch and an auxiliary MOSFET 4 for the auxiliary switch are disposed on the same chip. In this way, the self-turn-on phenomenon can be prevented, allowing the mounting of a low-side MOSFET 3 with a low threshold voltage and thereby significantly improving power conversion efficiency. The gate of the auxiliary MOSFET 4 is driven by the driver for the high-side MOSFET 2 , thereby eliminating the need for a new drive circuit and realizing the same pin configuration as existing products, which facilitates easy replacement.

Semiconductor device, DC/DC converter and power supply

This paper presents a novel side gate HiGT (High-conductivity IGBT) that incorporates historical changes of gate structures for planar and trench gate IGBTs. Side gate HiGT has a side-wall gate, and the opposite side of channel region for side-wall gate is covered by a thick oxide layer to reduce Miller capacitance (Cres). In addition, side gate HiGT has no floating p-layer, which causes the excess Vge overshoot. The proposed side gate HiGT has 75% smaller Cres than the conventional trench gate IGBT. The excess Vge overshoot during turn-on is effectively suppressed, and Eon + Err can be reduced by 34% at the same diode's recovery dv/dt. Furthermore, side gate HiGT has sufficiently rugged RBSOA and SCSOA.

Masaki Shiraishi

Papers

Semiconductor device and power supply system

Semiconductor device and manufacturing method of the same, and non-isolated DC/DC converter

Drive circuit and inverter for voltage driving type semiconductor device

Semiconductor device, DC/DC converter and power supply

Side gate HiGT with low dv/dt noise and low loss