This paper proposes a synthesis of different electrical methods used to estimate the temperature of power semiconductor devices. The following measurement methods are introduced: the voltage under low current levels, the threshold voltage, the voltage under high current levels, the gate-emitter voltage, the saturation current, and the switching times. All these methods are then compared in terms of sensitivity, linearity, accuracy, genericity, calibration needs, and possibility of characterizing the thermal impedance or the temperature during the operation of the converter. The measurement of thermo-sensitive parameters of wide bandgap semiconductors is also discussed.

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Temperature Measurement of Power Semiconductor Devices by Thermo-Sensitive Electrical Parameters—A Review

The introduction of enhancement-mode gallium-nitride-based power devices such as the eGaN FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the printed circuit board (PCB) layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET-based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This paper will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design, providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Understanding the Effect of PCB Layout on Circuit Performance in a High-Frequency Gallium-Nitride-Based Point of Load Converter

A power semiconductor module with its thermal resistance and overall size reduced Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader

Power semiconductor module

The introduction of enhancement mode gallium nitride based power devices such as the eGaN®FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with Silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the PCB layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This work will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter

This article reviews the design and evaluation of different DC-DC converter topologies for Battery Electric Vehicles (BEVs) and Plug-in Hybrid Electric Vehicles (PHEVs). The design and evaluation of these converter topologies are presented, analyzed and compared in terms of output power, component count, switching frequency, electromagnetic interference (EMI), losses, effectiveness, reliability and cost. This paper also evaluates the architecture, merits and demerits of converter topologies (AC-DC and DC-DC) for Fast Charging Stations (FCHARs). On the basis of this analysis, it has found that the Multidevice Interleaved DC-DC Bidirectional Converter (MDIBC) is the most suitable topology for high-power BEVs and PHEVs (> 10kW), thanks to its low input current ripples, low output voltage ripples, low electromagnetic interference, bidirectionality, high efficiency and high reliability. In contrast, for low-power electric vehicles (<10 kW), it is tough to recommend a single candidate that is the best in all possible aspects. However, the Sinusoidal Amplitude Converter, the Z-Source DC-DC converter and the boost DC-DC converter with resonant circuit are more suitable for low-power BEVs and PHEVs because of their soft switching, noise-free operation, low switching loss and high efficiency. Finally, this paper explores the opportunity of using wide band gap semiconductors (WBGSs) in DC-DC converters for BEVs, PHEVs and converters for FCHARs. Specifically, the future roadmap of research for WBGSs, modeling of emerging topologies and design techniques of the control system for BEV and PHEV powertrains are also presented in detail, which will certainly help researchers and solution engineers of automotive industries to select the suitable converter topology to achieve the growth of projected power density.

DC-DC Converter Topologies for Electric Vehicles, Plug-in Hybrid Electric Vehicles and Fast Charging Stations: State of the Art and Future Trends

A power MOS-FET is used as a high side switch transistor for a non-insulated DC/DC converter. An electrode section that serves as a source terminal of the power MOS-FET is connected to one outer lead and two outer leads via bonding wires respectively. The outer lead is an external terminal connected to a path for driving the gate. Each of the outer leads is an external terminal connected to a main current path. Owing to the connection of the main current path and the gate driving path in discrete form, the influence of parasitic inductance can be reduced and voltage conversion efficiency can be improved.

Semiconductor device and power supply system

A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the world's lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor. The lead frames and MOSFETs are connected with Cu leads, which reduce the spreading resistance of the MOSFET electrodes.

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor device including a DC-DC converter

This paper presents a system-in-package (SiP) that mounts an input capacitor for voltage regulators. The SiP has a low power loss of 3.8 W at a switching frequency of 1 MHz, input voltage of 12 V, and output current of 25 A. The parasitic inductance of this SiP is 56% that of the previously reported SiP, which had the input capacitor mounted on the printed circuit board, and this reduction is due to the short current loop from the input capacitor to the MOSFETs. As a result, the power loss can be reduced by 20% for the same spike voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the drain electrode of the high-side MOSFET and the source electrode of the low-side MOSFET to the mounted input capacitor. The authors also propose a way to estimate the parasitic inductance experimentally, not from a current measurement such as with a shunt resistor and a current probe, but from the ringing frequency when the high-side MOSFET is switched and the output capacitance C oss of the MOSFET being on the off state.

A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Tomoaki Uno

Papers

Semiconductor device and power supply system

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators

Semiconductor device including a DC-DC converter

A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

Semiconductor device and a manufacturing method of the same