M
Masamichi Akazawa
Researcher at Hokkaido University
Publications - 93
Citations - 1505
Masamichi Akazawa is an academic researcher from Hokkaido University. The author has contributed to research in topics: X-ray photoelectron spectroscopy & Passivation. The author has an hindex of 21, co-authored 89 publications receiving 1424 citations.
Papers
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Single-electron logic device based on the binary decision diagram
TL;DR: The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport and computer simulation shows that the designed circuits perform the logic operations correctly.
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Control of compound semiconductor–insulator interfaces by an ultrathin molecular‐beam epitaxy Si layer
TL;DR: Based on the disorder induced gap state (DIGS) model, an attempt is made to control the insulator-semiconductor (I-S) interfaces of GaAs and In0.53Ga0.47As by an ultrathin surface-oxidized silicon interface control layer (ICL) as discussed by the authors.
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Effect of a thin dielectric layer on terahertz transmission characteristics for metal hole arrays
TL;DR: This work measured zero-order transmission spectra of the 2D-MHAs by changing the thickness of the dielectric layer and found that the bandpass transmission peak shifted to the lower-frequency side with increasing layer thickness, owing to the change of the resonant frequency of the SPP.
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Characterization of electronic states at insulator/(Al)GaN interfaces for improved insulated gate and surface passivation structures of GaN-based transistors
Zenji Yatabe,Yujin Hori,Wan-Cheng Ma,Joel T. Asubar,Masamichi Akazawa,Taketomo Sato,Tamotsu Hashizume +6 more
TL;DR: In this article, the authors present a systematic characterization of electronic states at insulators/(Al)GaN interfaces, particularly focusing on insulator/AlGaN/GaN structures.
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Surface passivation of III–V semiconductors for future CMOS devices—Past research, present status and key issues for future
TL;DR: In this paper, a survey of surface passivation and MISFETs is made, and Fermi level pinning at insulator-semiconductor interface is discussed, and a brief review is made on recent approaches of interface control for high-k III-V MIS structures.