M
Masaru Ishizuka
Researcher at Toshiba
Publications - 37
Citations - 243
Masaru Ishizuka is an academic researcher from Toshiba. The author has contributed to research in topics: Thermal resistance & Heat transfer. The author has an hindex of 10, co-authored 37 publications receiving 236 citations.
Papers
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Proceedings ArticleDOI
Cooling performance of plate fins for multichip modules
TL;DR: In this paper, the authors evaluate the air cooling characteristics of plate fins for MCMs (multichip modules) with and without some spanwise space around the plate fins, and propose empirical equations for the Nusselt number and friction factor based on the numerical results.
Journal ArticleDOI
Development of prediction technique for cooling performance of finned heat sink in uniform flow
TL;DR: In this article, a numerical simulation was carried out on the flow and the temperature fields around a plate fin array subjected to a uniform flow, varying the ratio of fin length L to the half-pitch of fin s. The results showed that frictional resistance and heat transfer of the fin array showed excellent agreement with those for the developing flow between parallel plates with uniform inlet flow velocity equal to U/sub f/.
Proceedings ArticleDOI
Forced convection air cooling characteristics of plate fins for notebook personal computers
Hideo Iwasaki,Masaru Ishizuka +1 more
TL;DR: In this article, a three-dimensional laminar flow simulation was carried out in order to investigate forced convection air cooling characteristics of compact plate fin arrays expected to be used for cooling notebook personal computers under the condition for which the fin tips were shrouded and no spanwise space around the fins was provided.
Patent
Power semiconductor switching apparatus with heat sinks
Masaru Ishizuka,Yasuyuki Yokono,Asako Matsuura,Yoshio Kamei,Hiromichi Ohashi,Mitsuhiko Kitagawa,Tomiya Sasaki,Shigeki Monma +7 more
TL;DR: A semiconductor switching apparatus includes a member for radiating heat generated from semiconductor switches and for reducing a thermal stress as mentioned in this paper, and the lengths of gate electrode wires are equally set.