There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Phase-change materials are some of the most promising materials for data-storage applications. They are already used in rewriteable optical data storage and offer great potential as an emerging non-volatile electronic memory. This review looks at the unique property combination that characterizes phase-change materials. The crystalline state often shows an octahedral-like atomic arrangement, frequently accompanied by pronounced lattice distortions and huge vacancy concentrations. This can be attributed to the chemical bonding in phase-change alloys, which is promoted by p-orbitals. From this insight, phase-change alloys with desired properties can be designed. This is demonstrated for the optical properties of phase-change alloys, in particular the contrast between the amorphous and crystalline states. The origin of the fast crystallization kinetics is also discussed.

Phase-change materials for rewriteable data storage

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase Change Memory

Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Phase-change memory

We have developed the new "Yin-Yang" feedback technology for SRAM cells. This technology is applied to six-transistor cells and four-transistor cells, which are composed of transistors with the new D2G-SOI structure. At the 65-nm process node, these cells can operate at 0.7 V in mass-produced LSIs under real usage conditions. Max operating speeds are 300 MHz for the six-transistor and 200 MHz for the four-transistor cell. Leakage current of the four-transistor cell is about 1/1000 that of a conventional four-transistor cell. These cells provide a SRAM menu that allows us to optimally balance the requirements of various types of SRAM in low-power LSIs.

Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

Tunnel-leakage currents become the dominant form of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multierrors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultralow-power 16-Mb SRAM. A test chip fabricated by using 0.13-/spl mu/m CMOS technology showed per-cell standby-current values of 16.7 fA at 25/spl deg/C and 101.7 fA at 90/spl deg/C. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

SRAM cells with two P-well structure

This paper describes an investigation of cosmic-ray-induced multicell error behavior in SRAMs. A combination of device- and circuit-level simulation was used to show that a parasitic bipolar effect is responsible for such errors, and the underlying mechanism is what we call a battery effect. We have also demonstrated, for the first time, that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well taps (Nc). The results are used as the basis of an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multicell errors. The proposed guideline simply states that the allocation of memory cells to addresses should be based on consideration of the Nc. The architecture in its form reduces the soft error rate of an SRAM with Nc=16 by 88%.

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

We designed a logic-library-friendly SRAM array. The array uses rectangular-diffusion cell (RD cell) and delta-boosted-array-voltage scheme (DBA scheme). In the RD cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA scheme compensates it. Using the combination of RD cell and DBA scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency, 140-/spl mu/W power dissipation, and 0.9-/spl mu/A standby current.

Kenichi Osada

Papers

Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors

SRAM cells with two P-well structure

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme