International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Networks are a fundamental tool for understanding and modeling complex systems in physics, biology, neuroscience, engineering, and social science. Many networks are known to exhibit rich, lower-order connectivity patterns that can be captured at the level of individual nodes and edges. However, higher-order organization of complex networks—at the level of small network subgraphs—remains largely unknown. Here, we develop a generalized framework for clustering networks on the basis of higher-order connectivity patterns. This framework provides mathematical guarantees on the optimality of obtained clusters and scales to networks with billions of edges. The framework reveals higher-order organization in a number of networks, including information propagation units in neuronal networks and hub structure in transportation networks. Results show that networks exhibit rich higher-order organizational structures that are exposed by clustering based on higher-order connectivity patterns.

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Higher-order organization of complex networks

Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic circuit theory and in related disciplines such as electrical impedance tomography, smart grid monitoring, transient stability assessment, and analysis of power electronics. Kron reduction is also relevant in other physical domains, in computational applications, and in the reduction of Markov chains. Related concepts have also been studied as purely theoretic problems in the literature on linear algebra. In this paper we analyze the Kron reduction process from the viewpoint of algebraic graph theory. Specifically, we provide a comprehensive and detailed graph-theoretic analysis of Kron reduction encompassing topological, algebraic, spectral, resistive, and sensitivity analyses. Throughout our theoretic elaborations we especially emphasize the practical applicability of our results to various problem setups arising in engineering, computation, and linear algebra. Our analysis of Kron reduction leads to novel insights both on the mathematical and the physical side.

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Kron Reduction of Graphs With Applications to Electrical Networks

Consider a weighted and undirected graph, possibly with self-loops, and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to the self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a subset of nodes. The Kron reduction process is ubiquitous in classic circuit theory and in related disciplines such as electrical impedance tomography, smart grid monitoring, transient stability assessment in power networks, or analysis and simulation of induction motors and power electronics. More general applications of Kron reduction occur in sparse matrix algorithms, multi-grid solvers, finite--element analysis, and Markov chains. The Schur complement of a Laplacian matrix and related concepts have also been studied under different names and as purely theoretic problems in the literature on linear algebra. In this paper we propose a general graph-theoretic framework for Kron reduction that leads to novel and deep insights both on the mathematical and the physical side. We show the applicability of our framework to various practical problem setups arising in engineering applications and computation. Furthermore, we provide a comprehensive and detailed graph-theoretic analysis of the Kron reduction process encompassing topological, algebraic, spectral, resistive, and sensitivity analyses. Throughout our theoretic elaborations we especially emphasize the practical applicability of our results.

Kron Reduction of Graphs with Applications to Electrical Networks

Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.

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VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

Scaling of device dimensions down to nanometer range helps achieve unprecedented switching speed and multifunctional processing capabilities of nanoelectronic circuits and systems. However, interconnect constraints in the existing and emerging applications are expected to become the primary bottlenecks unless radical change is introduced in the design and technology of on-chip signal communication medium. In response to this demand, various novel and innovative interconnect solutions like carbon nanotube (CNT) are currently being explored as alternatives to metal wires. This paper proposes a unique structure of mixed CNT bundle with a specific arrangement of single-wall and multi-wall CNTs in the bundle. A comprehensive modeling and analysis of the conductance, inductance, and capacitance of the proposed mixed CNT bundle reveals that there will be no significant decrease in the overall conductance of the bundle, but the structural arrangement clearly reduces capacitive crosstalk between neighboring signal lines. Inductive crosstalk is seen to remain unchanged.

A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as VLSI Interconnection

A new design of silicon photonics ring resonator based biosensor for the detection of the diseased cell is proposed. The proposed label-free and high-Q ring resonator has the potential to exhibit high sensitivity and selectivity for detecting different cancer cells, such as leukemia, cervical cancer, and breast cancer. The parameters of the ring resonator are optimized to make the biosensor suitable for detecting cancer cells in the pinch of blood with the sensitivity of more than 200 nanometers per Refractive Index Unit (nm/RIU) and quality factor of 1200. Through the finite difference time domain (FDTD) method, it is observed that the resonant wavelength of a ring resonator can be increased by escalating the refractive index of the modal present on the surface of the ring resonator. The simulation and analysis demonstrate that the outline sensitivity and quality factor of the proposed biosensing platform are acceptable for the cancer cell level detection in the blood sample present on the surface of the resonator. The proposed design also shows sufficiently separated resonant peaks for different cancer cells that open the possibility of highly selective label-free cancer cell detection.

High-Quality Optical Ring Resonator-Based Biosensor for Cancer Detection

Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop error correction mechanisms at the architecture level. Utilizing this increased robustness, the clock frequencies of the circuits are pushed beyond the point of allowing full voltage swing. This increases the errors observed due to noise and other external factors. The resulting errors are then corrected through the error correction mechanisms. We first develop a realistic model for error probability in register files for a given clock frequency. Then, we present the overall architecture, which allows the error detection computation to be overlapped with other computation in the pipeline. We develop novel techniques that utilize the fact that at a given instance many physical registers are not used in superscalar processors. These underutilized registers are used to store the values of active registers. Our simulation results show that for a fixed architecture the access times to the registers can be reduced by as much as 80% while increasing the number of execution cycles by 0.12%. On the other hand, by reducing the register file access pipeline stages by 75%, the average number of execution cycles of SPEC applications can be reduced by 11.5%.

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Engineering over-clocking: reliability-performance trade-offs for high-performance register files

This paper illustrates the growing significance of self and mutual inductances by examining their effects on performance and characteristic issues like propagation delay, rise time, and overshoots. This paper introduces Elmore-like closed form solutions to analyze the behavior of integrated circuits in the presence of self and mutual inductances. The complexity of the expressions introduced here is linear with the number of elements in the interconnect network, and has Elmore delay accuracy characteristics. The propagation delay and overshoots estimated based on these formulae are within 15% of AS/X simulations for a wide range of interconnects from IBM's most recent CMOS technology.

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.

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Masud H. Chowdhury

Papers

A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as VLSI Interconnection

High-Quality Optical Ring Resonator-Based Biosensor for Cancer Detection

Engineering over-clocking: reliability-performance trade-offs for high-performance register files

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

Design of Ternary Logic and Arithmetic Circuits Using GNRFET