Recent research advocates asymmetric multi-core architectures, where cores in the same processor can have different performance. These architectures support single-threaded performance and multithreaded throughput at lower costs (e.g., die size and power). However, they also pose unique challenges to operating systems, which traditionally assume homogeneous hardware. This paper presents AMPS, an operating system scheduler that efficiently supports both SMP-and NUMA-style performance-asymmetric architectures. AMPS contains three components: asymmetry-aware load balancing, faster-core-first scheduling, and NUMA-aware migration. We have implemented AMPS in Linux kernel 2.6.16 and used CPU clock modulation to emulate performance asymmetry on an SMP and NUMA system. For various workloads, we show that AMPS achieves a median speedup of 1.16 with a maximum of 1.44 over stock Linux on the SMP, and a median of 1.07 with a maximum of 2.61 on the NUMA system. Our results also show that AMPS improves fairness and repeatability of application performance measurements.

/pdf/efficient-operating-system-scheduling-for-performance-2ka46htl3f.pdf

Efficient operating system scheduling for performance-asymmetric multi-core architectures

Heterogeneous architectures that integrate a mix of big and small cores are very attractive because they can achieve high single-threaded performance while enabling high performance thread-level parallelism with lower energy costs. Despite their benefits, they pose significant challenges to the operating system software. Thread scheduling is one of the most critical challenges.In this paper we propose bias scheduling for heterogeneous systems with cores that have different microarchitectures and performance.We identify key metrics that characterize an application bias, namely the core type that best suits its resource needs. By dynamically monitoring application bias, the operating system is able to match threads to the core type that can maximize system throughput. Bias scheduling takes advantage of this by influencing the existing scheduler to select the core type that bests suits the application when performing load balancing operations.Bias scheduling can be implemented on top of most existing schedulers since its impact is limited to changes in the load balancing code. In particular, we implemented it over the Linux scheduler on a real system that models microarchitectural differences accurately and found that it can improve system performance significantly, and in proportion to the application bias diversity present in the workload. Unlike previous work, bias scheduling does not require sampling of CPI on all core types or offline profiling. We also expose the limits of dynamic voltage/frequency scaling as an evaluation vehicle for heterogeneous systems.

http://eurosys2010.sigops-france.fr/slides/eurosys2010_session5_talk10.pdf

Bias scheduling in heterogeneous multi-core architectures

Cache sharing among processors is important for Chip Multiprocessors to reduce inter-thread latency, but also brings cache contention, degrading program performance considerably. Recent studies have shown that job co-scheduling can effectively alleviate the contention, but it remains an open question how to efficiently find optimal co-schedules. Solving the question is critical for determining the potential of a co-scheduling system. This paper presents a theoretical analysis of the complexity of co-scheduling, proving its NP-completeness. Furthermore, for a special case when there are two sharers per chip, we propose an algorithm that finds the optimal co-schedules in polynomial time. For more complex cases, we design and evaluate a sequence of approximation algorithms, among which, the hierarchical matching algorithm produces near-optimal schedules and shows good scalability. This study facilitates the evaluation of co-scheduling systems, as well as offers some techniques directly usable in proactive job co-scheduling.

/pdf/analysis-and-approximation-of-optimal-co-scheduling-on-chip-2cuxz2660n.pdf

Analysis and approximation of optimal co-scheduling on chip multiprocessors

With high-end systems featuring multicore/multithreaded processors and high component density, power-aware high-performance multithreading libraries become a critical element of the system software stack. Online power and performance adaptation of multithreaded code from within user-level runtime libraries is a relatively new and unexplored area of research. We present a user-level library framework for nearly optimal online adaptation of multithreaded codes for low-power, high-performance execution. Our framework operates by regulating concurrency and changing the processors/threads configuration as the program executes. It is innovative in that it uses fast, runtime performance prediction derived from hardware event-driven profiling, to select thread granularities that achieve nearly optimal energy-efficiency points. The use of predictors substantially reduces the runtime cost of granularity control and program adaptation. Our framework achieves performance and ED2 (energy-delay-squared) levels which are: i) comparable to or better than those of oracle-derived offline predictors; ii) significantly better than those of online predictors using exhaustive or localized linear search. The complete prediction and adaptation framework is implemented on a real multi-SMT system with Intel Hyperthreaded processors and embeds adaptation capabilities in OpenMP programs.

/pdf/online-power-performance-adaptation-of-multithreaded-jjzbdm4tm3.pdf

Online power-performance adaptation of multithreaded programs using hardware event-based prediction

A heterogeneous processor consists of cores that are asymmetric in performance and functionality. Such a design provides a cost-effective solution for processor manufacturers to continuously improve both single-thread performance and multi-thread throughput. This design, however, faces significant challenges in the operating system, which traditionally assumes only homogeneous hardware. This paper presents a comprehensive study of OS support for heterogeneous architectures in which cores have asymmetric performance and overlapping, but non-identical instruction sets. Our algorithms allow applications to transparently execute and fairly share different types of cores. We have implemented these algorithms in the Linux 2.6.24 kernel and evaluated them on an actual heterogeneous platform. Evaluation results demonstrate that our designs efficiently manage heterogeneous hardware and enable significant performance improvements for a range of applications.

/pdf/operating-system-support-for-overlapping-isa-heterogeneous-4cy93zg27a.pdf

Operating system support for overlapping-ISA heterogeneous multi-core architectures

Prior research has shown that single-ISA heterogeneous chip multiprocessors have the potential for greater performance and energy efficiency than homogeneous CMPs. However, restricting the cores to a single ISA removes an important opportunity for greater heterogeneity. To take full advantage of a heterogeneous-ISA CMP, however, we must be able to migrate execution among heterogeneous cores in order to adapt to program phase changes and changing external conditions (e.g., system power state).This paper explores migration on heterogeneous-ISA CMPs. This is non-trivial because program state is kept in an architecture-specific form; therefore, state transformation is necessary for migration. To keep migration cost low, the amount of state that requires transformation must be minimized. This work identifies large portions of program state whose form is not critical for performance; the compiler is modified to produce programs that keep most of their state in an architecture-neutral form so that only a small number of data items must be repositioned and no pointers need to be changed. The result is low migration cost with minimal sacrifice of non-migration performance.Additionally, this work leverages binary translation to enable instantaneous migration. When migration is requested, the program is immediately migrated to a different core where binary translation runs for a short time until a function call is reached, at which point program state is transformed and execution continues natively on the new core.This system can tolerate migrations as often as every 100 ms and still retain 95% of the performance of a system that does not do, or support, migration.

/pdf/execution-migration-in-a-heterogeneous-isa-chip-1oijemihyc.pdf

Execution migration in a heterogeneous-ISA chip multiprocessor

This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling, applied to this architecture, will attempt to balance the thread load across cores. This research demonstrates that such an approach eliminates one of the big advantages of this architecture - the ability to use unbalanced schedules to allocate the right amount of execution resources to each thread. However, accommodating unbalanced schedules creates several difficulties, the biggest being the fact that the search space of all schedules (both balanced and unbalanced) is much greater than that of the balanced schedules alone. This work proposes and evaluates scheduling policies that allow the system to identify and migrate toward good thread schedules, whether the best schedules are balanced or unbalanced.

/pdf/exploiting-unbalanced-thread-scheduling-for-energy-and-15scincyg9.pdf

Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors

This paper proposes a new runtime parallelization technique, based on a dynamic optimization framework, to automatically parallelize single-threaded legacy programs. It heavily leverages the optimistic concurrency of transactional memory. This work addresses a number of challenges posed by this type of parallelization and quantifies the trade-offs of some of the design decisions, such as how to select good loops for parallelization, how to partition the iteration space among parallel threads, how to handle loop-carried dependencies, and how to transition from serial to parallel execution and back. The simulated implementation of runtime parallelization shows a potential speedup of 1.36 for the NAS benchmarks and a 1.34 speedup for the SPEC 2000 CPU floating point benchmarks when using two cores for parallel execution.

/pdf/runtime-parallelization-of-legacy-code-on-a-transactional-rpyjqe0chk.pdf

Runtime parallelization of legacy code on a transactional memory system

As the microprocessor industry embraces multicore architectures, inherently parallel applications benefit directly as they easily transform into sets of homogeneous parallel threads. However, many applications do not t this model. These applications include legacy binaries compiled for a single thread of execution and inherently serial applications. The inability of these two kinds of applications to exploit multicore architectures has created a crisis for the microprocessor industry : customers have come to expect significant performance improvements in all of their application every processor generation, but recent multicore architectures have failed to meet those expectations for many applications. This dissertation explores ways in which these applications can run efficiently on multi core platforms. The performance of legacy binaries compiled for a single thread of execution can be improved through automatic parallelization. We introduce a new technique to automatically parallelize binaries as they are executing. The parallelization technique leverages the benefits of hardware transactional memory, a synchronization mechanism enabling optimistic concurrency. Our technique exploits this to parallelize code that a traditional parallelizing compiler would be unable to transform due to potential memory aliasing. Applications with fundamentally serial code can benefits from core customization. The more heterogeneous the cores are, the more likely that a given application will nd a core on which it runs efficiently. We investigate two forms of heterogeneity : that created on homogeneous hardware by unbalanced resource assignment, and heterogeneity created by hardware asymmetry. We first consider a homogeneous multicore system composed of multithreading cores. Often the best schedules on such a system are unbalanced. We propose a set of novel scheduling algorithms that consider unbalanced schedules to nd good application-to-core assignments. We consider objective functions of both performance and energy. We also explore how applications can benefit from diverse Isms by considering heterogeneous-ISA multicore systems. We propose a new technique to rapidly migrate a thread among cores of different Isms, allowing applications to take advantage of hardware heterogeneity for performance gain or energy savings

Matthew DeVuyst

Papers

Execution migration in a heterogeneous-ISA chip multiprocessor

Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors

Runtime parallelization of legacy code on a transactional memory system

Efficient Use of Execution Resources in Multicore Processor Architectures