"I hope that readers will learn to use the full expressibility and power of OpenMP. This book should provide an excellent introduction to beginners, and the performance section should help those with some experience who want to push OpenMP to its limits." --from the foreword by David J. Kuck, Intel Fellow, Software and Solutions Group, and Director, Parallel and Distributed Solutions, Intel Corporation OpenMP, a portable programming interface for shared memory parallel computers, was adopted as an informal standard in 1997 by computer scientists who wanted a unified model on which to base programs for shared memory systems. OpenMP is now used by many software developers; it offers significant advantages over both hand-threading and MPI. Using OpenMP offers a comprehensive introduction to parallel programming concepts and a detailed overview of OpenMP. Using OpenMP discusses hardware developments, describes where OpenMP is applicable, and compares OpenMP to other programming interfaces for shared and distributed memory parallel architectures. It introduces the individual features of OpenMP, provides many source code examples that demonstrate the use and functionality of the language constructs, and offers tips on writing an efficient OpenMP program. It describes how to use OpenMP in full-scale applications to achieve high performance on large-scale architectures, discussing several case studies in detail, and offers in-depth troubleshooting advice. It explains how OpenMP is translated into explicitly multithreaded code, providing a valuable behind-the-scenes account of OpenMP program performance. Finally, Using OpenMP considers trends likely to influence OpenMP development, offering a glimpse of the possibilities of a future OpenMP 3.0 from the vantage point of the current OpenMP 2.5. With multicore computer use increasing, the need for a comprehensive introduction and overview of the standard interface is clear. Using OpenMP provides an essential reference not only for students at both undergraduate and graduate levels but also for professionals who intend to parallelize existing codes or develop new parallel programs for shared memory computer architectures.

Using OpenMP: Portable Shared Memory Parallel Programming (Scientific and Engineering Computation)

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.

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A Survey and Evaluation of FPGA High-Level Synthesis Tools

A fleet management system for managing a fleet of encoded information reading (EIR) terminals can comprise one or more computers, a fleet management software module, and a payment processing software module in communication with the fleet management software module. The fleet management software module can be configured, responsive to receiving a customer initiated request, to generate an unlocking message upon processing a payment by the payment processing software module. The unlocking message can be provided by a bar code to be read by an EIR terminal, or by a bit stream to be transferred to an EIR terminal via network. Each EIR terminal can be configured to perform not more than a pre-defined number of EIR operations responsive to receiving the unlocking message.

Pre-paid usage system for encoded information reading terminals

We present the Colorwave algorithm, a simple, distributed, on-line algorithm for the reader collision problem in radio frequency identification (RFID) systems. RFID systems are increasingly being used in applications, such as those experienced in supply chain management, which require RFID readers to operate in close proximity to one another. Readers physically located near one another may interfere with one another's operation. Such reader collisions must be minimized to ensure the correct operation of the RFID system. The Colorwave algorithm yields on-line solutions that are near the optimal static solutions. The dynamic nature of the algorithm enables the RFID system to automatically adapt to changes in the system and in the operating environment of the system.

Color-wave : An anticollision algorithm for the reader collision problem

A mobile terminal including a display configured to display information; a short range communication module configured to exchange a signal with an external control device; and a controller configured to receive the signal from the external control device, determine a context at a timing point of receiving the signal, and control an operation corresponding to the signal to be performed in the determined context. Further, the operation includes at least one of activation/deactivation of the display, an activation/deactivation of a lock mode of the mobile terminal, a volume operation and a camera operation.

Mobile terminal and controlling method thereof

Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., implicit threads) from the sequential execution stream and speculatively executes them in parallel on multiple processor cores. These proposals augment a conventional multiprocessor, which employs explicit threading, with the ability to handle implicit threads. Current proposals focus on only implicitly-threaded code sections. This paper identifies, for the first time, the issues in combining explicit and implicit threading. We present the Multiplex architecture to combine the two threading models. Multiplex exploits the similarities between implicit and explicit threading, and provides a unified support for the two threading models without additional hardware. Multiplex groups a subset of protocol states in an implicitly-threaded CMP to provide a write-invalidate protocol for explicit threads.Using a fully-integrated compiler infrastructure for automatic generation of Multiplex code, this paper presents a detailed performance analysis for entire benchmarks, instead of just implicitly-threaded sections, as done in previous papers. We show that neither threading models alone performs consistently better than the other across the benchmarks. A CMP with four dual-issue CPUs achieves a speedup of 1.48 and 2.17 over one dual-issue CPU, using implicit-only and explicit-only threading, respectively. Multiplex matches or outperforms the better of the two threading models for every benchmark, and a four-CPU Multiplex achieves a speedup of 2.63. Our detailed analysis indicates that the dominant overheads in an implicitly-threaded CMP are speculation state overflow due to limited L1 cache capacity, and load imbalance and data dependences in fine-grain threads.

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Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor

This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.

A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption

The present invention is directed to a method and system for translating a high-level language (HLL) code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL which requires no modification in the original HLL source code, while supporting a cross call between software and hardware, and even recursive calls in hardware. The system includes: a HLL-to-HLL source translator which reads user programming directive from a translation-targeted high-level language code marked with the user directive, and separates the translation-targeted high-level language code into a hardware code part and a software code part; a main compiler which compiles the software code part; a HLL-to-HDL translator which includes the front-end and middle-end of the main compiler and a HDL backend; a main core which executes the compiled software code part; and a dedicated hardware which executes the HDL code.

System and method for translating high-level programming language code into hardware description language code

We present our effort to provide a comprehensive parallel programming environment for the OpenMP parallel directive language. This environment includes a parallel programming methodology for the OpenMP programming model and a set of tools (Ursa Minor and InterPol) that support this methodology. Our toolset provides automated and interactive assistance to parallel programmers in time-consuming tasks of the proposed methodology. The features provided by our tools include performance and program structure visualization, interactive optimization, support for performance modeling, and performance advising for finding and correcting performance problems. The presented evaluation demonstrates that our environment offers significant support in general parallel tuning efforts and that the toolset facilitates many common tasks in OpenMP parallel programming in an efficient manner.

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Parallel programming environment for OpenMP

Most implementations of accumulators, multipliers, or multiplier-accumulator units, operating in a finite integer ring, R(m), are based on ROM's or PLA's This paper proposes a full adder-based arithmetic unit, called an (FA)-based AU/sub m/, capable of performing both addition and general multiplication at the same time, in R(m) For all moduli, FA-based AU/sub m/'s are shown to execute much faster and have much less hardware complexity and smaller time-complexity products than ROM-based AU/sub m/'s For large values of m, they are also shown to be less complex and have smaller time-complexity products than ROM-based units, which are capable of performing multiplication only by a constant Since the proposed units use full adders as the basic building block, they result in easy-to-design, modular, and regular VLSI implementations >

Seon Wook Kim

Papers

Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor

A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption

System and method for translating high-level programming language code into hardware description language code

Parallel programming environment for OpenMP

Full adder-based arithmetic units for finite integer rings