Silicon germanium (SiGe) has moved from being a research material to accounting for a small but significant percentage of manufactured semiconductor devices. This percentage is predicted to increase substantially as SiGe begins to be used in complementary metal oxide semiconductor (CMOS) technology in the future to substantially improve performance. It is the development of Si/SiGe heterostructures which has enabled band structure and strain engineering allowing Si/SiGe to be used in many different ways to improve conventional microelectronic device performance along with allowing new concepts to be explored. This paper presents a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system. In particular, the important device technologies in mainstream microelectronics of the SiGe heterostructure bipolar transistor (HBT) and strained-Si CMOS will be reviewed before future device and optoelectronics concepts are explored.

https://iopscience.iop.org/article/10.1088/0268-1242/19/10/R02/pdf

Si/SiGe heterostructures: from material and physics to devices and circuits

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's) New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates

/pdf/digital-circuit-applications-of-resonant-tunneling-devices-393fsr9ny8.pdf

Digital circuit applications of resonant tunneling devices

The resonant tunneling diode (RTD) has been widely studied because of its importance in the field of nanoelectronic science and technology and its potential applications in very high speed/functionality devices and circuits. Even though much progress has been made in this regard, additional work is needed to realize the full potential of RTD's. As research on RTD's continues, we will try in this tutorial review to provide the reader with an overall and succinct picture of where we stand in this exciting field or research and to address the following questions: What makes RTD's so attractive? To what extent can RTD's be modeled for design purposes? What are the required and achievable device properties in terms of digital logic applications? To address these issues, we review the device operational principles, various modeling approaches, and major device properties. Comparisons among the various RTD physical models and major features of RTD's, resonant interband tunneling diodes, and Esaki tunnel diodes are presented. The tutorial and analysis provided in this paper may help the reader in becoming familiar with current research efforts, as well as to examine the important aspects in further RTD developments and their circuit applications.

/pdf/resonant-tunneling-diodes-models-and-properties-16lzfs8v3d.pdf

Resonant tunneling diodes: models and properties

Nanofabrication is playing an ever increasing role in science and technology on the nanometer scale and will soon allow us to build systems of the same complexity as found in nature. Conventional methods that emerged from microelectronics are now used for the fabrication of structures for integrated circuits, microelectro-mechanical systems, microoptics and microanalytical devices. Nonconventional or alternative approaches have changed the way we pattern very fine structures and have brought about a new appreciation of simple and low-cost techniques. We present an overview of some of these methods, paying particular attention to those which enable large-scale production of lithographic patterns. We preface the review with a brief primer on lithography and pattern transfer concepts. After reviewing the various patterning techniques, we discuss some recent application issues in the fields of microelectronics, optoelectronics, magnetism as well as in biology and biochemistry.

Nanofabrication: conventional and nonconventional methods.

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

/pdf/vlsi-implementations-of-threshold-logic-a-comprehensive-vqkiwr19v2.pdf

VLSI implementations of threshold logic-a comprehensive survey

This paper presents MOS-NDR, a new prototyping technique for multiple-valued logic circuits combining MOS transistors and multipeak negative differential-resistance (NDR) devices such as resonant-tunneling diodes (RTDs). MOS-NDR emulates the folded current-voltage characteristics of NDR devices such as RTDs using only NMOS transistors, MOS-NDR has enabled the development of a fully integrated multivalued signed-digit full adder (SDFA) circuit by means of a standard 0.6-micron CMOS process technology. The prototype has been fabricated and correct operation has been verified. The circuit dimensions are 123.75 by 38.7 microns, which is more than 15 times smaller than the area required by the equivalent hybrid RTD-CMOS prototype. The propagation delay of the hybrid RTD-CMOS design is estimated to be close to six times higher than that of the MOS-NDR implementation.

Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-/spl mu/m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differentiaI-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 /spl mu/m/sup 2/ and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation.

/pdf/cmos-implementation-of-a-multiple-valued-logic-signed-digit-13c75r7kad.pdf

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section. In the first embodiment, the output circuit section includes a plurality of FETs which perform second stage of latching such that the output of this section reflects the logic of the chosen inputs only at the occurrence of either a low-to-high transition or a high-to-low transition on the clock signal, but not both, depending on the chosen configuration of the flip-flop circuit. In a second embodiment, a D flip-flop circuit includes a latch circuit section which includes at least one NDR diode connected to the data output of the input circuit section and an output circuit section which also includes at least one NDR diode connected to the output of the output circuit section. In the second embodiment, the flip-flop circuit may use: 1) bistable NDR logic; 2) cascaded NDR latches; or 3) pseudo-bistable NDR logic with a true, single-phase clock.

High-speed, compact, edge-triggered, flip-flop circuit

In this paper we present a method for prototyping circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) devices that can enable us to realize large-scale digital circuits with negative differential-resistance (NDR) devices. Our method is based on designing CMOS circuits which can emulate the current-voltage (I-V) characteristics of RTDs. We demonstrate the effectiveness of our scheme by means of simulation and fabrication of an NDR shift register circuit.

Mayukh Bhattacharya

Papers

Digital circuit applications of resonant tunneling devices

Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

High-speed, compact, edge-triggered, flip-flop circuit

A prototyping technique for large-scale RTD-CMOS circuits