Patent
High-speed, compact, edge-triggered, flip-flop circuit
Reads0
Chats0
TLDR
In this article, a high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section.Abstract:
A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section. In the first embodiment, the output circuit section includes a plurality of FETs which perform second stage of latching such that the output of this section reflects the logic of the chosen inputs only at the occurrence of either a low-to-high transition or a high-to-low transition on the clock signal, but not both, depending on the chosen configuration of the flip-flop circuit. In a second embodiment, a D flip-flop circuit includes a latch circuit section which includes at least one NDR diode connected to the data output of the input circuit section and an output circuit section which also includes at least one NDR diode connected to the output of the output circuit section. In the second embodiment, the flip-flop circuit may use: 1) bistable NDR logic; 2) cascaded NDR latches; or 3) pseudo-bistable NDR logic with a true, single-phase clock.read more
Citations
More filters
Patent
Fractional-N synthesizer with improved noise performance
TL;DR: In this article, a fractional sequence generator with a plurality of cascaded accumulators whose carry-out-upon-overflow is provided over a multiplicity of recombination paths and selective delays to an adder is considered.
Patent
Dynamic circuits having improved noise tolerance and method for designing same
Li Ding,Pinaki Mazumder +1 more
TL;DR: In this article, a number of different dynamic circuits having improved noise tolerance and a method for designing the same are provided, which include a power supply node and a precharge node.
Patent
Fractional-N digital modulation with analog IQ interface
TL;DR: In this paper, analog and digital I and Q data streams are generated by specially configured conversion circuits, the outputs of which are applied to a F-N synthesizer to modulate the synthesizer.
Patent
Accumulator with programmable full-scale range
TL;DR: In this paper, a multi-accumulator structure was proposed for a fractional sequence generator for use in a F-N synthesizer, where the contents of a n-bit accumulator in each accumulator are augmented by a function of the programmable denominator value upon a carry-out of the associated nbit adder in that accumulator.
Patent
SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof
TL;DR: In this article, the SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes, which can be applied to very high speed digital circuits.
References
More filters
Journal ArticleDOI
High-speed CMOS circuit technique
Jiren Yuan,Christer Svensson +1 more
TL;DR: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.
Patent
High-speed flip flop circuit with master latching circuit free from influence of slave latching circuit
TL;DR: A flip flop circuit comprises a master latching circuit having a first transmission gate responsive to a clock signal and the complementary clock signal for transferring a data bit to a first positive feedback loop, and a slave latching circuits having a second transmitter and a second receiver responsive to both the clock and complementary clock signals and complementarily shifted between on and off states with respect to the first transmitter as mentioned in this paper.
Patent
Ultra fast shift register using resonant tunnel diodes
Hao Tang,Tom P. E. Broekaert +1 more
TL;DR: In this paper, a high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) to achieve a bistable operating state.
Patent
Tunnel diode shift register utilizing tunnel diode coupling
TL;DR: In this article, a shift register with a first bistable latching circuit and a second clock voltage pulse source is presented, which can switch from a low voltage state to a high voltage state in response to receiving an input current and a first clock voltage pulses.
Patent
Logic circuit for bistable D-dynamic flip-flops
TL;DR: In this article, a logic circuit for dynamic D-flip-flop includes five n-channel MOS transistors and five p-channel transistors, and it works correctly without any additional delay element or capacitor.