Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (SRAM) cell design with reduced write delay. The proposed eight-transistor (8T) CNTFET-based SRAM cell improves read/write static noise margin by 1.98×/1.25×, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The write access time and leakage power of the proposed cell are improved by 1.90× and 2.14×, respectively, compared to the conventional 6T design. The proposed design parameters are also compared with two already presented 8T SRAM cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model. 

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

Optimal Design and Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor

Analysis and Design of Novel Doping Free Silicon Nanotube TFET with High-density Meshing Using ML for Sub Nanometre Technology Nodes

Performance Analysis of Doping Less Nanotube Tunnel Field Effect Transistor for High Speed Applications

Robust Approach Towards Wearable Power Efficient Transistors with Low Subthreshold Swing

Implementation and Performance Evaluation of Ferroelectric Negative Capacitance FET

Performance Evaluation of FinFET Device Under Nanometer Regime for Ultra-low Power Applications

Design and analysis of CMOS based 6T SRAM cell at different technology nodes

Carbon Nanotube Field Effect Transistor (CNTFET) has proved to be very beneficial for VLSI circuit designs in the nano scale range due to its amazing properties than MOSFETs. As we reduce the gate length of the device to below 45nm, we see a lot of changes in its parameters such as stability of the cell reduces, power consumption and delay increases which are different from the traditional MOSFETs. This becomes a serious issue when we try to take traditional MOSFETs scale down from this technology node. The main aim of this paper is to design CNTFET 6T SRAM memory cell which consumes less power and is highly stable at 32nm technology node. The Stanford model files have proved to be very good for the CNTFET devices, which simulates on 32 nm technology nodes in HSPICE tool. The results shown in this paper clearly indicate that the stability enhances by approx. 27.55% of the CNTFET SRAM cell with 37.44% improvement in the power consumption. Explicit analysis of the results shows that CNTFET based 6T SRAM cell has improved power consumption, less delay and high stability with improved read & write noise margin than conventional 6T SRAM cell.

Meenakshi Devi

Papers

Implementation and Performance Evaluation of Ferroelectric Negative Capacitance FET

Performance Evaluation of FinFET Device Under Nanometer Regime for Ultra-low Power Applications

Design and analysis of CMOS based 6T SRAM cell at different technology nodes

Design and Stability analysis of CNTFET based SRAM cell