Two-dimensional (2D) materials have attracted increasing research interest because of the abundant choice of materials with diverse and tunable electronic, optical, and chemical properties. Moreover, 2D material based heterostructures combining several individual 2D materials provide unique platforms to create an almost infinite number of materials and show exotic physical phenomena as well as new properties and applications. To achieve these high expectations, methods for the scalable preparation of 2D materials and 2D heterostructures of high quality and low cost must be developed. Chemical vapor deposition (CVD) is a powerful method which may meet the above requirements, and has been extensively used to grow 2D materials and their heterostructures in recent years, despite several challenges remaining. In this review of the challenges in the CVD growth of 2D materials, we highlight recent advances in the controlled growth of single crystal 2D materials, with an emphasis on semiconducting transition meta...

Chemical Vapor Deposition Growth and Applications of Two-Dimensional Materials and Their Heterostructures

The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

Graphene and two-dimensional materials for silicon technology.

Two-dimensional (2D) materials have attracted tremendous research interest since the breakthrough of graphene. Their unique optical, electronic, and mechanical properties hold great potential for harnessing them as key components in novel applications for electronics and optoelectronics. Their atomic thickness and exposed huge surface even make them highly designable and manipulable, leading to the extensive application potentials. What's more, after acquiring the qualification for being the candidate for next-generation devices, the assembly of 2D materials monomers into mass or ordered structure is also of great importance, which will determine their ultimate industrialization. By designing the monomers and regulating their assembling behavior, the exploration of 2D materials toward the next-generation circuits can be spectacularly achieved. In this review, we will first overview the emerging 2D materials and then offer a clear guideline of varied physical and chemical strategies for tuning their properties. Furthermore, assembly strategies of 2D materials will also be included. Finally, challenges and outlooks in this promising field are featured on the basis of its current progress.

Exploring Two-Dimensional Materials toward the Next-Generation Circuits: From Monomer Design to Assembly Control

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications.

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor-molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

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A microprocessor based on a two-dimensional semiconductor

Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc–dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cel...

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

Recently, monolayers of van der Waals materials, including transition metal dichalcogenides (TMDs), are considered ideal building blocks for constructing 2D artificial lattices and heterostructures. Heterostructures with multijunctions of more than two monolayer TMDs are intriguing for exploring new physics and materials properties. Obtaining in-plane heterojunctions of monolayer TMDs with atomically sharp interfaces is very significant for fundamental research and applications. Currently, multistep synthesis for more than two monolayer TMDs remains a challenge because decomposition or compositional alloying is thermodynamically favored at the high growth temperature. Here, a multistep chemical vapor deposition (CVD) synthesis of the in-plane multijunctions of monolayer TMDs is presented. A low growth temperature synthesis is developed to avoid compositional fluctuations of as-grown TMDs, defects formations, and interfacial alloying for high heterointerface quality and thermal stability of monolayer TMDs. With optimized parameters, atomically sharp interfaces are successfully achieved in the synthesis of in-plane artificial lattices of the WS2 /WSe2 /MoS2 at reduced growth temperatures. Growth behaviors as well as the heterointerface quality are carefully studied in varying growth parameters. Highly oriented strain patterns are found in the second harmonic generation imaging of the TMD multijunctions, suggesting that the in-plane heteroepitaxial growth may induce distortion for unique material symmetry.

Synthesis of In-Plane Artificial Lattices of Monolayer Multijunctions.

A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer ( 20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (T sub 200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at V DD =0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.

Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D + IC

https://onlinelibrary.wiley.com/doi/epdf/10.1002/adma.201870043

Monolayer Multijunctions: Synthesis of In‐Plane Artificial Lattices of Monolayer Multijunctions (Adv. Mater. 7/2018)

Moiré lattice in artificially stacked monolayers of two-dimensional (2D) materials effectively modulates the electronic structures of materials, which is widely highlighted. Formation of the electronic Moiré superlattice promises the prospect of uniformity among different moiré cells across the lattice, enabling a new platform for novel properties, such as unconventional superconductivity, and scalable quantum emitters. Recently, epitaxial growth of the monolayer transition metal dichalcogenide (TMD) is achieved on the sapphire substrate by chemical vapor deposition (CVD) to realize scalable growth of highly-oriented monolayers. However, fabrication of the scalable Moiré lattice remains challenging due to the lack of essential manipulation of the well-aligned monolayers for clean interface quality and precise twisting angle control. Here, scalable and highly-oriented monolayers of TMD are realized on the sapphire substrates by using the customized CVD process. Controlled growth of the epitaxial monolayers is achieved by promoting the rotation of the nuclei-like domains in the initial growth stage, enabling aligned domains for further grain growth in the steady-state stage. A full coverage and distribution of the highly-oriented domains are verified by second-harmonic generation (SHG) microscopy. By developing the method for clean monolayer manipulation, hetero-stacked bilayer (epi-WS2/epi-MoS2) is fabricated with the specific angular alignment of the two major oriented monolayers at the edge direction of 0°/ ± 60°. On account of the optimization for scalable Moiré lattice with a high-quality interface, the observation of interlayer exciton at low temperature illustrates the feasibility of scalable Moiré superlattice based on the oriented monolayers. 

https://nanoscalereslett.springeropen.com/track/pdf/10.1186/s11671-022-03670-y

Meng-Hsi Chuang

Papers

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

Synthesis of In-Plane Artificial Lattices of Monolayer Multijunctions.

Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D + IC

Monolayer Multijunctions: Synthesis of In‐Plane Artificial Lattices of Monolayer Multijunctions (Adv. Mater. 7/2018)

Scalable Moiré Lattice with Oriented TMD Monolayers