Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any
printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order
to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more
larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns
(including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the
feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks.
Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a
programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an
optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated
process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect
qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

Wafer inspection as alternative approach to mask defect qualification

A new die-to-database high-resolution reticle defect inspection platform, TeraScanHR, has been developed for advanced production use with the 45nm logic node, and extendable for development use with the 32nm node (also the comparable memory nodes). These nodes will use predominantly ArF immersion lithography although EUV may also be used. According to recent surveys, the predominant reticle types for the 45nm node are 6% simple tri-tone and COG. Other advanced reticle types may also be used for these nodes including: dark field alternating, Mask Enhancer, complex tri-tone, high transmission, CPL, etc. Finally, aggressive model based OPC will typically be used which will include many small structures such as jogs, serifs, and SRAF (sub-resolution assist features) with accompanying very small gaps between adjacent structures. The current generation of inspection systems is inadequate to meet these requirements. The architecture and performance of the new TeraScanHR reticle inspection platform is described. This new platform is designed to inspect the aforementioned reticle types in die-to-database and die-to-die modes using both transmitted and reflected illumination. Recent results from field testing at two of the three beta sites are shown (Toppan Printing in Japan and the Advanced Mask Technology Center in Germany). The results include applicable programmed defect test reticles and advanced 45nm product reticles (also comparable memory reticles). The results show high sensitivity and low false detections being achieved. The platform can also be configured for the current 65nm, 90nm, and 130nm nodes.

Field results from a new die-to-database reticle inspection platform

A new die-to-database high-resolution reticle defect inspection system has been developed for the 45nm logic node and extendable to the 32nm node (also the comparable memory nodes). These nodes will use predominantly 193nm immersion lithography although EUV may also be used. According to recent surveys, the predominant reticle types for the 45nm node are 6% simple tri-tone and COG. Other advanced reticle types may also be used for these nodes including: dark field alternating, Mask Enhancer, complex tri-tone, high transmission, CPL, EUV, etc. Finally, aggressive model based OPC will typically be used which will include many small structures such as jogs, serifs, and SRAF (sub-resolution assist features) with accompanying very small gaps between adjacent structures. The current generation of inspection systems is inadequate to meet these requirements. The architecture and performance of a new die-to-database inspection system is described. This new system is designed to inspect the aforementioned reticle types in die-to-database and die-to-die modes. Recent results from internal testing of the prototype systems are shown. The results include standard programmed defect test reticles and advanced 45nm and 32nm node reticles from industry sources. The results show high sensitivity and low false detections being achieved.

/pdf/results-from-a-new-die-to-database-reticle-inspection-2zts558s7g.pdf

Results from a new die-to-database reticle inspection platform

As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) [1]. Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D [2] [3] [4] only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) [6].

Enhanced photomask quality control by 2D structures monitoring using auto image-to-layout method on advanced 28nm technology node or beyond

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers’ continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask’s physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask’s performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year’s work at AMTC to assess the full implementation of SWaP as an enhancement to mask characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization and qualification.

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.

Wafer fab mask qualification techniques and limitations

High resolution mask inspection in advanced wafer fabs is a necessity. Initial and progressive mask defect problem still remains an industry wide mask reliability issue. Defect incidences and its criticality vary significantly among the type of masks, technology node and layer, fab environment and mask usage. A usage and layer based qualification strategy for masks in production need to be adopted in wafer fabs. 

With the help of a high-resolution direct reticle inspection, early detection of critical and also non-critical defects at high capture rates is possible. A high-resolution inspection that is capable of providing necessary sensitivity to critical emerging defects (near edge) is very important in advanced nodes. At the same time, a way to disposition (make a go / no-go decision) on these defective masks is also very important. As the impact of these defects will depend on not only their size, but also on their transmission and MEEF, various defect types and characteristics have to be considered. 

In this technical report the adoption of such a high-resolution mask inspection system in wafer fab production is presented and discussed. Data on this work will include inspection results from advanced masks, layer and product based inspection pixel assignment, defect disposition and overall wafer fab strategies in day-to-day production towards mask inspection.

Michael Lang

Papers

Wafer fab mask qualification techniques and limitations

High-resolution mask inspection in advanced fab