Protection systems and methods provide for protecting one or more personal computers (“PCs”) and/or other intermittently or persistently network accessible devices or processes from undesirable or otherwise malicious operations of Java TN applets, ActiveX™ controls, JavaScript™ scripts, Visual Basic scripts, add-ins, downloaded/uploaded programs or other “Downloadables” or “mobile code” in whole or part. A protection engine embodiment provides for monitoring information received, determining whether received information does or is likely to include executable code, and if so, causes mobile protection code (MPC) to be transferred to and rendered operable within a destination device of the received information. An MPC embodiment further provides, within a Downloadable-destination, for initiating the Downloadable, enabling malicious Downloadable operation attempts to be received by the MPC, and causing (predetermined) corresponding operations to be executed in response to the attempts.

Malicious mobile code runtime monitoring system and methods

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Apparatuses and methods for performing compare operations using sensing circuitry

Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Division operations for memory

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

Independently addressable memory array address spaces

A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

System & method of linking separately compiled simulations

The present invention is a method and apparatus for runtime binding of object members. The invention extends the late binding functionality allowed for virtual functions by static compiled programming languages like C, C++, JAVA, to all class members and class methods (functions) of all objects (classes), including virtual functions. According to one embodiment access to any member or method of any object results in a runtime search to find the member or method and to verify that the member or method exists. This eliminates the need to type cast to get access to members of a derived class. Each member of a class has an access control level associated with it, and according to another embodiment this access control protocol is honored by the runtime search to make sure that the user has access to only public members, and not private members.

Method and apparatus for runtime binding of object members

Systems and methods consistent with the present invention allocate memory of a memory array by partitioning the memory array into subheaps dedicated to frequently used memory blocks To this end, the system collects memory statistics on memory usage patterns to determine memory block sizes most often used in the memory array The system uses these statistics to partition the memory array into a main heap and at least one memory subheap The system then allocates or deallocate memory of the memory array using the memory subheap Furthermore, the system allocates memory of the memory subheap only for memory blocks having one of the memory block sizes most often used in the memory array

System and method for allocating memory by partitioning a memory

A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Method and apparatus for simulation processor

Methods and systems consistent with the invention allocate memory of a memory array using a free list. The free list is a list of pointers to blocks of free memory located within the memory array. First, the system determines whether to sort the free list based on deallocation activity of the memory array. If so, the system sorts the free list according to the memory size of the blocks of free memory pointed to by the free list. The system then allocates memory of the memory array for the storage of data using the sorted free list.

David S. Allison

Papers

System & method of linking separately compiled simulations

Method and apparatus for runtime binding of object members

System and method for allocating memory by partitioning a memory

Method and apparatus for simulation processor

System and method for heuristically allocating memory