A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Method of depositing an amorphous carbon layer

The progressively decreasing feature size of the circuit components has tremendously increased the need for the global surface planarization of the various thin film layers that constitute the integrated circuit (IC). Global planarization, being one of the major solutions to meet the demands of the industry, needs to be achieved following the most efficient polishing procedure. Chemical mechanical polishing (CMP) is the planarization method that has been selected by the semiconductor industry today. CMP, an ancient process used for glass polishing, was adopted first as a microelectronic fabrication process by IBM in the 80 s for SiO2 polishing. To achieve efficient planarization at miniaturized device dimensions, there is a need for a better understanding of the physics, chemistry and the complex interplay of tribo-mechanical phenomena occurring at the interface of the pad and wafer in presence of the fluid slurry medium. In spite of the fact that CMP research has grown by leaps and bounds, there are some teething problems associated with CMP process such as delamination, microscratches, dishing, erosion, corrosion, inefficient post-CMP clean, etc.; research on which is still developing. The fundamental understanding of the CMP is highly necessary to characterize, optimize and model the process. The CMP process is ready to make a positive impact on 30% of the US$ 135 billion global semiconductor market. This paper presents an overview of CMP process in general, the science and mechanism of polishing, different metal and dielectric CMP processes. The impact of consumables on the CMP process, post-CMP cleaning, modeling of different CMP processes as well as the future trends are also discussed.

Chemical mechanical planarization for microelectronics applications

A slurry for use in chemical-mechanical polishing of a metal layer comprising high purity fine metal oxide particles uniformly dispersed in a stable aqueous medium.

Chemical mechanical polishing slurry for metal layers

A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.

Removable amorphous carbon CMP stop

The present invention provides a carbon based etch stop, such as a diamond like amorphous carbon, having a low dielectric constant and a method of forming a dual damascene structure. The low k etch stop is preferably deposited between two dielectric layers and patterned to define the underlying interlevel contacts/vias. The second or upper dielectric layer is formed over the etch stop and patterned to define the intralevel interconnects. The entire dual damascene structure is then etched in a single selective etch process which first etches the patterned interconnects, then etches the contact/vias past the patterned etch stop. The etch stop has a low dielectric constant relative to a conventional SiN etch stop, which minimizes the capacitive coupling between adjacent interconnect lines. The dual damascene structure is then filled with a suitable conductive material such as aluminum or copper and planarized using chemical mechanical polishing.

Micheal Leach

Papers

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing