A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Method of depositing an amorphous carbon layer

The progressively decreasing feature size of the circuit components has tremendously increased the need for the global surface planarization of the various thin film layers that constitute the integrated circuit (IC). Global planarization, being one of the major solutions to meet the demands of the industry, needs to be achieved following the most efficient polishing procedure. Chemical mechanical polishing (CMP) is the planarization method that has been selected by the semiconductor industry today. CMP, an ancient process used for glass polishing, was adopted first as a microelectronic fabrication process by IBM in the 80 s for SiO2 polishing. To achieve efficient planarization at miniaturized device dimensions, there is a need for a better understanding of the physics, chemistry and the complex interplay of tribo-mechanical phenomena occurring at the interface of the pad and wafer in presence of the fluid slurry medium. In spite of the fact that CMP research has grown by leaps and bounds, there are some teething problems associated with CMP process such as delamination, microscratches, dishing, erosion, corrosion, inefficient post-CMP clean, etc.; research on which is still developing. The fundamental understanding of the CMP is highly necessary to characterize, optimize and model the process. The CMP process is ready to make a positive impact on 30% of the US$ 135 billion global semiconductor market. This paper presents an overview of CMP process in general, the science and mechanism of polishing, different metal and dielectric CMP processes. The impact of consumables on the CMP process, post-CMP cleaning, modeling of different CMP processes as well as the future trends are also discussed.

Chemical mechanical planarization for microelectronics applications

A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.

Logical view with granular access to exchange data managed by a modular data and storage management system

A slurry for use in chemical-mechanical polishing of a metal layer comprising high purity fine metal oxide particles uniformly dispersed in a stable aqueous medium.

Chemical mechanical polishing slurry for metal layers

An improved high density interconnect structure may include electronic components mounted on both sides of its substrate or a substrate which is only as thick as the semiconductor chips which reduces the overall structure thickness to the thickness of the semiconductor chips plus the combined thickness of the high density interconnect structure's dielectric and conductive layers In the two-sided structures, feedthroughs, which are preferably hermetic, provide connections between opposite sides of the substrate Substrates of either of these types may be stacked to form a three-dimensional structure Means for connecting between adjacent substrates are preferably incorporated within the boundaries of the stack rather than on the outside surface thereof

Compact high density interconnect structure

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymer overlays with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin bonded to the surface of the layer. Multilevel structures are taught along with a self-aligned sealing and wiring process.

Sealing and stress relief layers and use thereof

A multilayered thin film structure for attaching input/output pins to a ceramic substrate, and method of making the thin film structure are disclosed. A thin adhesion layer, which can suitably be a refractory metal such as titanium, vanadium, chromium or tantalum, is first formed on the surface of the substrate. A thick stress reducing layer of soft metal such as copper, silver, nickel, aluminum, gold or iron is subsequently formed over the adhesion layer. To prevent the soft metal from reacting with subsequently brazed gold-tin pin eutectic alloy, a reaction barrier layer which can be titanium or zirconium is then deposited over the soft stress reducing metal cushion layer. The process is completed by finally depositing a gold layer over the reaction barrier layer.

Multilayer thin film metallurgy for pin brazing

A layer of zirconium can be used as an adhesion layer between a ceramic or polyimide substrate and subsequently applied metallic layers. Following the zirconium layer, copper can be deposited followed by a reaction barrier layer and a wettable surface layer such as gold. This type of structure can be used for pin bracing, chip joining, and/or wire connections.

Zirconium as an adhesion material in a multi-layer metallic structure

A multilayered thin film metallurgy for brazing input/­output pins to a ceramic substrate is disclosed. A thin adhesion layer (22), which can suitably be a refractory metal such as titanium, vanadium, chromium or tantalum, is first formed on the surface of the substrate (10). A thick stress reducing layer (24) of soft metal such as copper, silver, nickel, aluminum, gold or iron is subsequently formed over the adhesion layer. To prevent the soft metal from reacting with subsequently brazed gold-tin pin eutectic alloy, a reaction barrier layer (28) which can be titanium or zirconium is then deposited over the soft stress reducing metal cushion layer. The process is com­pleted by finally depositing a gold layer (30) over the reaction barrier layer.

Walter Frederick Lange

Papers

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Sealing and stress relief layers and use thereof

Multilayer thin film metallurgy for pin brazing

Zirconium as an adhesion material in a multi-layer metallic structure

Multilayered thin film metallurgy for brazing input/output pins to a ceramic substrate