M
Mimi Xie
Researcher at University of Texas at San Antonio
Publications - 47
Citations - 575
Mimi Xie is an academic researcher from University of Texas at San Antonio. The author has contributed to research in topics: Computer science & Overhead (computing). The author has an hindex of 12, co-authored 32 publications receiving 354 citations. Previous affiliations of Mimi Xie include University of Pittsburgh & Oklahoma State University–Stillwater.
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Proceedings ArticleDOI
Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor
TL;DR: This paper presents a consistency aware checkpointing scheme that ensures correctness for all checkpoints and efficiently identifies all possible inconsistency positions in programs and inserts auxiliary code to ensure correctness.
Proceedings ArticleDOI
FTRANS: energy-efficient acceleration of transformers using FPGA
Bingbing Li,Santosh Pandey,Haowen Fang,Yanjun Lyv,Ji Li,Jieyang Chen,Mimi Xie,Lipeng Wan,Hang Liu,Caiwen Ding +9 more
TL;DR: This paper proposes an efficient acceleration framework, Ftrans, for transformer-based large scale language representations, which includes enhanced block-circulant matrix (BCM)-based weight representation to enable model compression on large-scale language representations at the algorithm level with few accuracy degradation.
Proceedings ArticleDOI
Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems
TL;DR: In this paper, the authors proposed replacement and checkpoint policies for SRAM and NVM based hybrid cache in NVPs whose execution is interrupted frequently, and the experimental results show that the proposed architectures and polices outperform existing cache architectures for NVP.
Proceedings ArticleDOI
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system
TL;DR: This work proposes to analyze the application program and determine efficient backup positions, by which the necessary non-volatile register file size can be significantly reduced, and delivers an average of 62.9% reduction on non-Volatile registerfile size for stack backup, with negligible storage overheads.
Journal ArticleDOI
Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems
TL;DR: An integer linear programming formulation and a polynomial-time algorithm, the software wear-leveling algorithm, are proposed to achieve wear leveling without hardware overhead and can reduce the number of writes on the most-written addresses by more than 80% when compared with a greedy algorithm.