M
Miroslav N. Velev
Researcher at Ariès
Publications - 65
Citations - 2179
Miroslav N. Velev is an academic researcher from Ariès. The author has contributed to research in topics: Formal verification & Boolean satisfiability problem. The author has an hindex of 26, co-authored 65 publications receiving 2162 citations. Previous affiliations of Miroslav N. Velev include Carnegie Mellon University & Georgia Institute of Technology.
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Journal ArticleDOI
Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors
TL;DR: The SAT-checkers Chaff and BerkMin are identified as significantly outperforming the rest of the SAT tools when evaluating the Boolean correctness formulae in the formal verification of superscalar and VLIW microprocessors.
Journal ArticleDOI
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
TL;DR: In this paper, Burch and Dill presented two methods to translate the logic of equality with uninterpreted functions (EUF) into propositional logic and applied them to verify pipelined processors with load, store and branch instructions.
Posted Content
Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
TL;DR: Positive equality allows us to overcome the experimental blow-up experienced previously when verifying microprocessors with load, store, and branch instructions and two methods to translate formulas in EUF into propositional logic are presented.
Proceedings ArticleDOI
Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction
TL;DR: The Burch and Dill flushing technique is extended for formal verification of microprocessors and ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions are shown.
Proceedings ArticleDOI
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors
TL;DR: This work compares SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors and identifies one SAT- checker that significantly outperforms the rest.