Showing papers by "Mohamed I. Elmasry published in 2009"

Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits

Abstract: In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop(TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively.

A New Loss Compensation Technique for CMOS Distributed Amplifiers

Abstract: This brief presents a circuit technique to compensate for the metal and substrate loss of the on-chip transmission lines (TLs), and, consequently, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). An eight-stage DA suitable for 40-Gb/s optical communication is devised and implemented in a 0.13-mum CMOS process. The DA achieves a flat gain of 10 dB from dc to 44 GHz with an input and output matching better than -8 dB. The measured noise figure varies from 2.5 to 7.5 dB with the amplifier's band. The proposed DA dissipates 103 mW from two 1-V and 1.2-V dc supplies.

Total Power Modeling in FPGAs Under Spatial Correlation

Abstract: This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.

Comparative analysis of process variation impact on flip-flops soft error rate

Abstract: Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.

The impact of timing yield improvement under process variation on flip-flops soft error rate

Abstract: In deeply pipelined synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Due to CMOS technology scaling, increased process variations result in a large delay variability causing unacceptable loss in the timing yield. Several variation tolerant techniques are introduced to mitigate this variability challenge by improving the timing yield. In the mean time, devices are getting smaller, faster, and operating at lower supply voltages. These reduced capacitances and power supply voltages combined with the increased chip density to perform more functionality increase the soft errors susceptibility and make it one of the essential design challenges. Moreover, there are many flip-flops topologies that vary in their relative performance and power consumption which make the selection decision very difficult to flip-flops designers especially under variability and soft errors challenges. Therefore, a comparative analysis between these different flip-flops topologies considering these scaling challenges is beneficial to guide the flip-flops designers in selecting the best topology for their specific application constraints. This paper presents a comparative analysis of the timing yield improvement impact on flip-flops soft error rate by using the STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. Then, they are compared for the soft error susceptibility. Finally, it is shown that the timing yield improvement improves the flip-flops soft error immunity significantly.