BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Many critical electronic design automation (EDA) problems suffer from the curse of dimensionality, i.e., the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g., 3-D field solvers discretizations and multirate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g., full-chip routing/placement and circuit sizing), or extensive process variations (e.g., variability /reliability analysis and design for manufacturability). The computational challenges generated by such high-dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents “tensor computation” as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Near-threshold computing (NTC) poses stringent constraints on designing reliable circuits, as degradations have a magnified impact at lower supply voltages ( $V_{\text {dd}}$ ) compared with super-threshold supply voltages. While phenomena, such as bias temperature instability (BTI) scale down with $V_{\text {dd}}$ , mitigate their magnified impact with reduced degradations and, thus, have little impact on NTC reliability. Process variation (PV) and random telegraph noise (RTN) do not scale with $V_{\text {dd}}$ and, therefore, become key reliability challenges in NTC. On the other hand, in super-threshold computing (STC), PV and BTI are the dominant phenomena, as BTI induces considerable degradations at nominal $V_{\text {dd}}$ and PV imposes large enough shifts to matter at any supply voltage. Therefore, to allow $V_{\text {dd}}$ -scaling from super-to near-threshold, we need to consider all of BTI, RTN, and PV. Ergo, we present a unified RTN and BTI model that models their shared physical origin and is validated against experimental data across a wide voltage range. Our unified model and PV model capture the joint impact of RTN, BTI, and PV within a probabilistic reliability estimation for NTC and STC circuits. We employed our proposed model to analyze the reliability of SRAM cells showing how taking error correction codes into account is able to mitigate the deleterious effects of BTI, RTN, and PV by 36% compared with unprotected circuits.

Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV

As feature sizes of transistors began to approach atomic levels, aging effects have become one of major concerns when it comes to reliability. Recently, aging effects have become a subject to voltage scaling as the latter entered the sub-μs regime. Hence, aging shifted from a sole long-term (as treated by state-of-the-art) to a short and long-term reliability challenge. This paper interrelates both aging and voltage scaling to explore and quantify for the first time the short-term effects of aging. We propose “aging-awareness” with respect to voltage scaling which is indispensable to sustain runtime reliability. Otherwise, transient errors, caused by the short-term effects of aging, may occur. Compared to state-of-the-art, our aging-aware voltage scaling optimizes for both short-term and long-term aging effects at marginal guardband overhead.

Aging-aware voltage scaling

Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

BSIM compact models have served industry for more than a decade starting with BSIM3 and later BSIM4 and BSIMSOI. Here we will briefly discuss the ongoing work on current and future device models in BSIM group. BSIM6 is the next generation bulk RF MOSFET Model which uses charge based core with physical models adapted from BSIM4. Model fulfills all symmetry tests and shows correct slopes for harmonics. The BSIM-CMG and BSIM-IMG are the surface potential based models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Models include all read device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.

Mohammed A. Karim

Papers

BSIM — Industry standard compact MOSFET models