M
Moongon Jung
Researcher at Georgia Institute of Technology
Publications - 24
Citations - 861
Moongon Jung is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Three-dimensional integrated circuit & Chip. The author has an hindex of 14, co-authored 24 publications receiving 830 citations. Previous affiliations of Moongon Jung include Intel.
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Book ChapterDOI
3D-MAPS: 3D Massively parallel processor with stacked memory
Dae Hyun Kim,Krit Athikulwongse,Michael B. Healy,Mohammad M. Hossain,Moongon Jung,Ilya Khorosh,Gokul Kumar,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Shreepad Panth,Mohit Pathak,Minzhen Ren,Guanhao Shen,Taigon Song,Dong Hyuk Woo,Xin Zhao,Joungho Kim,Ho Choi,Gabriel H. Loh,Hsien-Hsin Lee,Sung Kyu Lim +22 more
TL;DR: 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM.
Journal ArticleDOI
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
TL;DR: An efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs are discussed.
Proceedings ArticleDOI
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
TL;DR: An efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3-D integrated circuits (ICs).
Proceedings ArticleDOI
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
Michael B. Healy,Krit Athikulwongse,Rohan Goel,Mohammad M. Hossain,Dae Hyun Kim,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Moongon Jung,Brian Ouellette,Mohit Pathak,Hemant Sane,Guanhao Shen,Dong Hyuk Woo,Xin Zhao,Gabriel H. Loh,Hsien-Hsin S. Lee,Sung Kyu Lim +18 more
TL;DR: The design and analysis of3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology is described.
Journal ArticleDOI
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)
Dae Hyun Kim,Krit Athikulwongse,Michael B. Healy,Mohammad M. Hossain,Moongon Jung,Ilya Khorosh,Gokul Kumar,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Shreepad Panth,Mohit Pathak,Minzhen Ren,Guanhao Shen,Taigon Song,Dong Hyuk Woo,Xin Zhao,Joungho Kim,Ho Choi,Gabriel H. Loh,Hsien-Hsin S. Lee,Sung Kyu Lim +22 more
TL;DR: The architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology are described.