D
Dae Hyun Kim
Researcher at Georgia Institute of Technology
Publications - 152
Citations - 3261
Dae Hyun Kim is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Dram & Three-dimensional integrated circuit. The author has an hindex of 29, co-authored 146 publications receiving 2730 citations. Previous affiliations of Dae Hyun Kim include Samsung & Seoul National University.
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Proceedings ArticleDOI
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks
Amirali Boroumand,Saugata Ghose,Youngsok Kim,Rachata Ausavarungnirun,Eric Shiu,Rahul Thakur,Dae Hyun Kim,Aki Kuusela,Allan Knies,Parthasarathy Ranganathan,Onur Mutlu +10 more
TL;DR: This work comprehensively analyzes the energy and performance impact of data movement for several widely-used Google consumer workloads, and finds that processing-in-memory (PIM) can significantly reduceData movement for all of these workloads by performing part of the computation close to memory.
Proceedings ArticleDOI
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
TL;DR: AVATAR is proposed, a VRT-aware multirate refresh scheme that adaptively changes the refresh rate for different rows at runtime based on current VRT failures, and provides a time to failure in the regime of several tens of years while reducing refresh operations by 62%-72%.
Proceedings ArticleDOI
A study of Through-Silicon-Via impact on the 3D stacked IC layout
TL;DR: A new force-directed 3D gate-level placement that efficiently handles TSV usage, and an algorithm that assigns TSVs to nets to complete routing that involves TSVs are presented.
Book ChapterDOI
3D-MAPS: 3D Massively parallel processor with stacked memory
Dae Hyun Kim,Krit Athikulwongse,Michael B. Healy,Mohammad M. Hossain,Moongon Jung,Ilya Khorosh,Gokul Kumar,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Shreepad Panth,Mohit Pathak,Minzhen Ren,Guanhao Shen,Taigon Song,Dong Hyuk Woo,Xin Zhao,Joungho Kim,Ho Choi,Gabriel H. Loh,Hsien-Hsin Lee,Sung Kyu Lim +22 more
TL;DR: 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM.
Proceedings ArticleDOI
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
TL;DR: This paper proposes ArchShield, an architectural framework that employs runtime testing to identify faulty DRAM cells and efficiently tolerate error-rates as higher as 10−4 (100x higher than ECC alone), causes less than 2% performance degradation, and still maintains 1-bit error tolerance against soft errors.