3D-MAPS: 3D Massively parallel processor with stacked memory

doi:10.1007/978-1-4419-9542-1_20

Book ChapterDOI

3D-MAPS: 3D Massively parallel processor with stacked memory

Dae Hyun Kim, +22 more

- pp 188-190

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TLDR

3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM.

Abstract:

Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5×5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

Citations

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NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

Seth H. Pugsley, +7 more

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