The design and development of wearable biosensor systems for health monitoring has garnered lots of attention in the scientific community and the industry during the last years. Mainly motivated by increasing healthcare costs and propelled by recent technological advances in miniature biosensing devices, smart textiles, microelectronics, and wireless communications, the continuous advance of wearable sensor-based systems will potentially transform the future of healthcare by enabling proactive personal health management and ubiquitous monitoring of a patient's health condition. These systems can comprise various types of small physiological sensors, transmission modules and processing capabilities, and can thus facilitate low-cost wearable unobtrusive solutions for continuous all-day and any-place health, mental and activity status monitoring. This paper attempts to comprehensively review the current research and development on wearable biosensor systems for health monitoring. A variety of system implementations are compared in an approach to identify the technological shortcomings of the current state-of-the-art in wearable biosensor solutions. An emphasis is given to multiparameter physiological sensing system designs, providing reliable vital signs measurements and incorporating real-time decision support for early detection of symptoms or context awareness. In order to evaluate the maturity level of the top current achievements in wearable health-monitoring systems, a set of significant features, that best describe the functionality and the characteristics of the systems, has been selected to derive a thorough study. The aim of this survey is not to criticize, but to serve as a reference for researchers and developers in this scientific area and to provide direction for future research improvements.

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A Survey on Wearable Sensor-Based Systems for Health Monitoring and Prognosis

DC–DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which fundamental energy storing elements (inductors and capacitors) and/or transformers in conjunction with switch(es) and diode(s) are utilized in the circuit. These techniques include switched capacitor (charge pump), voltage multiplier, switched inductor/voltage lift, magnetic coupling, and multistage/-level, and each has its own merits and demerits depending on application, in terms of cost, complexity, power density, reliability, and efficiency. To meet the growing demand for such applications, new power converter topologies that use the above voltage-boosting techniques, as well as some active and passive components, are continuously being proposed. The permutations and combinations of the various voltage-boosting techniques with additional components in a circuit allow for numerous new topologies and configurations, which are often confusing and difficult to follow. Therefore, to present a clear picture on the general law and framework of the development of next-generation step-up dc–dc converters, this paper aims to comprehensively review and classify various step-up dc–dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc–dc converters are presented and summarized with comparative study of different voltage-boosting techniques.

/pdf/step-up-dc-dc-converters-a-comprehensive-review-of-voltage-6dlytctzg2.pdf

Step-Up DC–DC Converters: A Comprehensive Review of Voltage-Boosting Techniques, Topologies, and Applications

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

A new design for an energy harvesting device is proposed in this paper, which enables scavenging energy from radiofrequency (RF) electromagnetic waves. Compared to common alternative energy sources like solar and wind, RF harvesting has the least energy density. The existing state-of-the-art solutions are effective only over narrow frequency ranges, are limited in efficiency response, and require higher levels of input power. This paper has a twofold contribution. First, we propose a dual-stage energy harvesting circuit composed of a seven-stage and ten-stage design, the former being more receptive in the low input power regions, while the latter is more suitable for higher power range. Each stage here is a modified voltage multiplier, arranged in series and our design provides guidelines on component choice and precise selection of the crossover operational point for these two stages between the high (20 dBm) and low power (-20 dBm) extremities. Second, we fabricate our design on a printed circuit board to demonstrate how such a circuit can run a commercial Mica2 sensor mote, with accompanying simulations on both ideal and non-ideal conditions for identifying the upper bound on achievable efficiency. With a simple yet optimal dual-stage design, experiments and characterization plots reveal approximately 100% improvement over other existing designs in the power range of -20 to 7 dBm.

https://repository.library.northeastern.edu/files/neu:1340/fulltext.pdf

Design Optimization and Implementation for RF Energy Harvesting Circuits

Current wireless technologies, such as wireless body area networks and wireless personal area networks, provide promising applications in medical monitoring systems to measure specified physiological data and also provide location-based information, if required. With the increasing sophistication of wearable and implantable medical devices and their integration with wireless sensors, an ever-expanding range of therapeutic and diagnostic applications is being pursued by research and commercial organizations. This paper aims to provide a comprehensive review of recent developments in wireless sensor technology for monitoring behaviour related to human physiological responses. It presents background information on the use of wireless technology and sensors to develop a wireless physiological measurement system. A generic miniature platform and other available technologies for wireless sensors have been studied in terms of hardware and software structural requirements for a low-cost, low-power, non-invasive and unobtrusive system.

https://iopscience.iop.org/article/10.1088/0967-3334/29/11/R01/pdf

Wireless body sensor networks for health-monitoring applications.

This paper presents a design methodology for an ultra-low-power (ULP) and ultra-low-voltage (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed and a new biasing metric for ULV and ULP designs in deep-submicrometer CMOS technologies is introduced. Series inductive peaking in the feedback loop is analyzed and employed to enhance the bandwidth and noise performance of the LNA. Exploiting the new biasing metric, the design methodology, and series inductive peaking in the feedback loop, a 0.5 V, 0.75-mW broadband LNA with a current reuse scheme is implemented in a 90-nm CMOS technology. Measurement results show 12.6-dB voltage gain, 0.1–7-GHz bandwidth, 5.5-dB NF, −9-dBm IIP $_{3}$ , and −18-dB P1dB while occupying 0.23 mm $^{2}$ .

A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13- $\mu {\text {m}}~1$ P8M CMOS technology and occupies only $0.0052~{\text {mm}}^{2}$ . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of −10 dBm and 0.1–-2.2 GHz bandwidth (BW), while consuming only 400 $\mu {\text {A}}$ from a 1-V supply.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This paper presents an overview of the ultra-wideband (UWB) technology for wireless communications systems. Following a brief review of the UWB basic principles, the characteristics of application specific UWB wireless systems are described. Design principles and challenges of UWB wireless systems, with an emphasis on monolithic implementations are discussed. Trade-offs between performance, power consumption, and technology choices are addressed. Examples of state-of-the-art UWB circuits and systems are presented.

Ultra-wideband (UWB) communications systems: an overview

This work examines the use of a forward body biasing (FBB) scheme to mitigate output conductance degradation due to short channel effects in ultra-low voltage (ULV) circuits with no additional power consumption. It is shown that FBB boosts the output resistance of a transistor such that the intrinsic gain reduction due to low-supply voltages can be compensated. This technique is then used to implement a low-noise amplifier (LNA) tailored for ultra-low power (ULP) and ULV applications. The proposed LNA uses common-gate (CG) NMOS transistors as input devices in a complementary current-reuse structure. Low-power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor. Moreover, a separate FBB scheme is exploited to tune the feedback coefficient. An inductive $g_m$ -boosting technique is used to increase the bandwidth of the LNA without additional power consumption. The proposed LNA is implemented in an IBM $0.13\ \upmu \text{m}$ 1P8M CMOS technology and occupies $0.39\ \text{mm}^2$ . The measured LNA has a 14 dB gain, 4 dB minimum noise figure, IIP3 of $-10\ \text{dBm}$ , and 0.6–4.2 GHz bandwidth, while consuming only $500\ \upmu$ A from a 0.5 V supply. The LNA operates with supplies as low as 0.4 V while maintaining good performance.

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 $\upmu \text{W}$ 0.6–4.2 GHz Current-Reuse CMOS LNA

A highly integrated 1.7-2.0 GHz digitally programmable frequency synthesizer using a MEMS resonator as its reference is presented. Due to the dimensions of the MEMS device (e.g., 25 mum by 114 mum), the entire system with a total area of 6.25 mm2 can be housed in a small standard chip package. This considerably reduces the form factor and cost of the system, compared to using an external crystal as a reference. The MEMS resonators are clamped-clamped beams fabricated using a CMOS-compatible process. The main structural layer is made of silicon carbide, which provides the resonators with higher power handling capabilities and higher operating frequencies, compared to silicon. The resonators are electrostatically and thermally tunable - an 8.4% frequency tuning is demonstrated for a 9 MHz resonator. The 100 nm vertical transducer gaps of the resonators allow the use of electrostatic actuation voltages as low as 2 V. An integrated high gain-bandwidth trans-impedance amplifier (TIA) is combined with a resonator to generate the synthesizer's input reference signal. The TIA employs automatic gain control to mitigate the inherent low power handling capabilities and the non-linearities of the MEMS device, thus minimizing their effect on phase noise. The fractional- N synthesizer employs a 3rd-order 20-bit delta-sigma modulator to deliver a theoretical output resolution of ~ 11 Hz, in order to allow for high output frequency stability when used with an appropriate feedback loop. A fully integrated on-chip dual path loop filter is used to maintain a high level of system integration. With a supply voltage of 2 V, the phase noise for a 1.8 GHz output frequency and a ~12 MHz reference signal is -122 dBc/Hz at a 600 kHz offset, and -137 dBc/Hz at a 3 MHz offset.

Mourad N. El-Gamal

Papers

A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

Ultra-wideband (UWB) communications systems: an overview

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 $\upmu \text{W}$ 0.6–4.2 GHz Current-Reuse CMOS LNA

A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator