A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

TLDR: The ULV circuit design challenges are discussed and a new biasing metric for ULV and ULP designs in deep-submicrometer CMOS technologies is introduced and series inductive peaking in the feedback loop is analyzed and employed to enhance the bandwidth and noise performance of the LNA.

Abstract: This paper presents a design methodology for an ultra-low-power (ULP) and ultra-low-voltage (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed and a new biasing metric for ULV and ULP designs in deep-submicrometer CMOS technologies is introduced. Series inductive peaking in the feedback loop is analyzed and employed to enhance the bandwidth and noise performance of the LNA. Exploiting the new biasing metric, the design methodology, and series inductive peaking in the feedback loop, a 0.5 V, 0.75-mW broadband LNA with a current reuse scheme is implemented in a 90-nm CMOS technology. Measurement results show 12.6-dB voltage gain, 0.1–7-GHz bandwidth, 5.5-dB NF, −9-dBm IIP $_{3}$ , and −18-dB P1dB while occupying 0.23 mm $^{2}$ .