Strained-semiconductor-on-insulator device structures

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded SIl-xGex(x increases from 0 to y) is deposited on a first silicone substrate, followed by deposition of a relaxed Sil-yGey layer, a thin strained Sil-zGez layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Sil-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Sil-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Sil-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

Process for producing semiconductor article using graded epitaxial growth

Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Hybrid fin field-effect transistor structures and related methods

The growth of Si1-xGex quantum wells with high Ge composition (x>0.5) on Si(001) substrates by MBE is of great interest both for HMOS device applications and fundamental research. One of the possibilities to obtain a high Ge content Si1-xGex channel for mobile carriers, while retaining its strain, is to grow a relaxed Si1-yGey buffer layer on an underlying Si substrate. Such a buffer is termed a virtual substrate (VS), which is a constituent of SiGe metamorphic heterostructures. The effect of annealing on the structure of the Si(001)/VS/Si0.7Ge0.3/Si0.2Ge0.8/Si0.7Ge0.3 heterostructures was studied by grazing angle of incidence RBS. The thickness of the Si0.2Ge0.8 channel is inhomogeneous, which makes the analysis of the data by traditional means very hard. We have developed a model whereby the influence of the thickness inhomogeneity of each layer in the apparent energy resolution as a function of depth can be calculated. Automatic fits to the data were performed, and the roughness parameters, that is, the standard deviation of the thickness inhomogeneity of the relevant layers, were obtained, together with the thickness and stoichiometry of each layer. The results are compared with TEM and high resolution XRD experiments.

N. Franco

Papers

RBS ANALYSIS OF MBE GROWN SiGe/(001)Si HETEROSTRUCTURES WITH THIN HIGH Ge CONTENT SiGe CHANNELS FOR HMOS TRANSISTORS