Journal ArticleDOI
RBS ANALYSIS OF MBE GROWN SiGe/(001)Si HETEROSTRUCTURES WITH THIN HIGH Ge CONTENT SiGe CHANNELS FOR HMOS TRANSISTORS
N.P. Barradas,A. D. Sequeira,N. Franco,Maksym Myronov,O. A. Mironov,P. J. Phillips,Evan H. C. Parker +6 more
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In this article, the effect of annealing on the structure of the Si(001)/VS/Si0.7Ge0.3 heterostructures was studied by grazing angle of incidence RBS.Abstract:
The growth of Si1-xGex quantum wells with high Ge composition (x>0.5) on Si(001) substrates by MBE is of great interest both for HMOS device applications and fundamental research. One of the possibilities to obtain a high Ge content Si1-xGex channel for mobile carriers, while retaining its strain, is to grow a relaxed Si1-yGey buffer layer on an underlying Si substrate. Such a buffer is termed a virtual substrate (VS), which is a constituent of SiGe metamorphic heterostructures. The effect of annealing on the structure of the Si(001)/VS/Si0.7Ge0.3/Si0.2Ge0.8/Si0.7Ge0.3 heterostructures was studied by grazing angle of incidence RBS. The thickness of the Si0.2Ge0.8 channel is inhomogeneous, which makes the analysis of the data by traditional means very hard. We have developed a model whereby the influence of the thickness inhomogeneity of each layer in the apparent energy resolution as a function of depth can be calculated. Automatic fits to the data were performed, and the roughness parameters, that is, the standard deviation of the thickness inhomogeneity of the relevant layers, were obtained, together with the thickness and stoichiometry of each layer. The results are compared with TEM and high resolution XRD experiments.read more
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References
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Journal ArticleDOI
Simulated annealing analysis of Rutherford backscattering data
TL;DR: In this article, the combinatorial optimization simulated annealing algorithm is applied to the analysis of Rutherford backscattering data, which is fully automatic and does not require time-consuming human intervention.
Journal ArticleDOI
Self-limitation in the surface segregation of Ge atoms during Si molecular beam epitaxial growth
TL;DR: In this article, the surface segregation of Ge atoms in the Si epitaxial overlayers arising from the surface bond geometry on Si(100) during molecular beam epitaxy has been investigated theoretically.
Journal ArticleDOI
Si1−xGex/Si multiple quantum well infrared detector
TL;DR: In this article, a long-wavelength infrared detector is demonstrated using Si1−xGex/Si multiple quantum wells for the first time, and a broad peak in the photoresponse is observed near 9 μm with a full width at half maximum of about 80 meV which provides the response in the 6-12 μm range.
Journal ArticleDOI
SiGe HBTs and HFETs
U. Konig,H. Dämbkes +1 more
TL;DR: SiGe is just on an upswing and outstanding performance was even demonstrated, e.g. high frequencies above 100 GHz, low noise below 0.5 dB at 2 GHz, high transconductances around 400 mS/mm as discussed by the authors.
Journal ArticleDOI
SiGe heterostructure CMOS circuits and applications
Evan H. C. Parker,Terry E. Whall +1 more
TL;DR: In this article, a review of the 300 k electron and hole mobilities in Si/SeGe heterostructures and the potential applications of these materials in CMOS technology are discussed.