Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.

Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

A common framework for interface-trap (NIT) generation involving broken equivSi-H and equivSi-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress. Holes (from inversion layer for pMOSFET NBTI, from channel due to impact ionization, and from gate poly due to anode-hole injection or valence-band hole tunneling for nMOSFET HCI) break equivSi-H bonds, whose time evolution is governed by either one-dimensional (NBTI or FN) or two-dimensional (HCI) reaction-diffusion models. Hot holes break equivSi-O bonds during both FN and HCI stress. Power-law time exponent of NIT during stress and recovery of NIT after stress are governed by relative contribution of broken equivSi-H and equivSi-O bonds (determined by cold- and hot-hole densities) and have important implications for lifetime prediction under NBTI, FN, and HCI stress conditions

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On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small.

Experimental evidence of inelastic tunneling in stress-induced leakage current

A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model.

A new I-V model for stress-induced leakage current including inelastic tunneling

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assisted tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction.

N. Yasuda

Papers

Experimental evidence of inelastic tunneling in stress-induced leakage current

A new I-V model for stress-induced leakage current including inelastic tunneling