Patent
Semiconductor device and fabrication method thereof
TLDR
In this article, a gate electrode is formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode.Abstract:
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.read more
Citations
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Patent
Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Patent
Contact Structure of Semiconductor Device
TL;DR: In this paper, the authors describe a contact structure for a semiconductor device consisting of a substrate comprising a major surface and a cavity below the major surface, wherein a strained material in the cavity is different from a lattice constant of the substrate.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
Method of Fabricating Semiconductor Device
TL;DR: In this paper, the bottom surface of the semiconductor wafer is ground to decrease a thickness of the wafer, and a reforming region is formed in the loaded wafer under the groove by irradiating a first laser through wafer chuck.
Patent
Method for Fabricating Semiconductor Device
TL;DR: In this article, a method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress, was proposed.
References
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Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Patent
Semiconductor transistor having a stressed channel
TL;DR: In this article, a process for manufacturing an improved PMOS semiconductor transistor is described, where the source and drain films are made of an alloy of silicon and germanium.
Patent
Device structure and method for reducing silicide encroachment
TL;DR: In this article, the authors describe a semiconductor device which has an electrode with a first thickness and a silicide layer having a second thickness is formed on the electrode, and a sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the width of the silicide.
Patent
Novel transistor with ultra shallow tip and method of fabrication
TL;DR: In this paper, a novel transistor with a low resistance ultra shallow tip region (214) and its method of fabrication was presented, which has a source/drain extension or tip region comprising an ultra shallow region, which extends beneath the gate electrode and a raised region.