Hiroshi Morioka

TL;DR: In this paper, a micro structure manufacturing method is proposed, which includes the steps of: (a) preparing an etching object having an etch target film, provided with a lower mask layer and an upper hard mask layer stacked on the etching target film.

TL;DR: In this paper, a new process flow which selectively forms SELS only on the nMOS gate was developed to solve wafer bending problem, and a high performance 37nm gate n-MOSFET and 45nm gate pMOS-FET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A/A//spl m and 690/spl m/A-spl mm at V/sub dd/=1V/I/sub off/=100nA/m, respectively.

TL;DR: In this article, the resist pattern is formed by coating a substrate with a photosensitive resist material and performing an exposure and a development, and a front layer of a side face and an upper surface of the resist surface is etched by a plasma of a mixture gas containing at least one first gas selected from the group consisting of He, Ne, Ar, Xe, Kr, CO, CO 2 and N 2, and an SO 2 gas.

TL;DR: In this paper, the authors improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure and achieved a high performance 30 nm/33 nm gate nMOSFET with a drive current of 937/1000 muA/mum.

TL;DR: In this article, a 25 nm gate CMOSFET for the 65 nm node is reported, where the authors successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc) both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration.