H. Kokura

TL;DR: In this paper, a new process flow which selectively forms SELS only on the nMOS gate was developed to solve wafer bending problem, and a high performance 37nm gate n-MOSFET and 45nm gate pMOS-FET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A/A//spl m and 690/spl m/A-spl mm at V/sub dd/=1V/I/sub off/=100nA/m, respectively.

TL;DR: In this paper, the authors improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure and achieved a high performance 30 nm/33 nm gate nMOSFET with a drive current of 937/1000 muA/mum.

TL;DR: In this article, a 25 nm gate CMOSFET for the 65 nm node is reported, where the authors successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc) both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration.

TL;DR: In this paper, a high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance reduction.

TL;DR: In this article, the impact of vertical gate scaling on dopant activation in poly-Si gate and device performance is investigated, and the authors demonstrate high performance 35 nm gate length CMOSFETs for 65 nm technology node.