Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20I%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

This paper deals with the measurement and modeling of on-chip interconnect inductance in a VLSI chip fabricated using a sub-100 nm copper (Cu) CMOS process. A test chip was designed and fabricated in a 90 nm process node, to study the inductive effects, with various inductive return paths, including substrate, co-planar structures, power grids, and random structures. S parameter measurements were made on these structures to extract wire inductance and skin effect. It was observed that the presence of CMP dummy metal fills influences the inductive behavior and skin effect of the Cu process. Inductive effects for Cu interconnects are then compared with previous studies on aluminum (Al) interconnect at 130 nm. This is followed by a discussion on the significance of inductance effects in sub-100 nm X architecture chip design.

http://ieeexplore.ieee.org/iel5/9849/31034/01452281.pdf

Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

This paper discusses the accurate modeling of resistance R, inductance L and capacitance C in sub-100nm process node and their impacts on high frequency effects such as delay, crosstalk, and power/ground bounce. Models of interconnect (wire) resistances increase due to electron scattering at the surface and grain boundaries, and coupling capacitance of high aspect ratio interconnects for sub100nm process nodes are presented. It is observed from test chip measurement that the skin effect and inductive effects of Cu interconnect at high frequencies exhibit different behaviors compared to Al interconnect, presumably because of the presence of CMP dummy metal fills. It is shown that the incorporation of frequency dependent R and L is essential in the modeling and characterization of high frequency effects for high speed ULSI circuits.

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Modeling and Characterization of High Frequency Effects in ULSI Interconnects

The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition times. The accurate modeling of inductance behavior is thus essential for high speed VLSI designs. Recently X architecture has been introduced to reduce overall IC interconnect length by using diagonal wirings pervasively, resulting in smaller die sizes and higher performance. Although the resistance and capacitance of diagonal wires and their modeling are well understood, the characterization and modeling studies of diagonal wire inductance remain scarce. In this paper, the authors study the inductance effects of diagonal wiring, specifically inductance with return loop through diagonal (X Architecture) and Manhattan power grids. Both self and mutual inductance of Manhattan and diagonal wirings in the presence of various power grids are obtained using both FastHenry simulations and on-chip measurements. Results show that both self and mutual inductance values of diagonal signal line(s) are invariant with respect to their placement relative to the power grid. We observe that measurements done on an actual test chip agree fairly well with simulation data. This makes inductance modeling in X Architecture designs easier compared to Manhattan design, and X Architecture design has an advantage over Manhattan design from inductance perspective

https://www.computer.org/csdl/pds/api/csdl/proceedings/download-article/12OmNzAohWu/pdf

On-Chip Inductance in X Architecture Enabled Design

The impact of reduced polysilicon doping concentration N p on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as N p is reduced. The performance degradation gets compounded when the gate oxide thickness t ox is reduced, and/or substrate concentration N b is increased. For a given t ox and non-degenerate value of N p , lowering the channel length helps to reduce the polydepletion effect and hence circuit performance degradation. However, reducing the power supply, for low power operation, enhances the polydepletion effect.

http://ieeexplore.ieee.org/iel5/5435650/5435651/05435738.pdf

Impact of Polysilicon Depletion Effect on Circuit Performance for 0.35μ CMOS Technology

The X Architecture is a new way of orienting the interconnect on an integrated circuit using diagonal pathways, as well as the traditional right-angle, or Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, the X Architecture can provide substantial improvements in chip performance, power consumption and cost. Members of the X Initiative semiconductor supply chain consortium have demonstrated the production worthiness of the X Architecture at the 130-nm and 90-nm process technology nodes. This paper presents an assessment of the manufacturing readiness of the X Architecture for the 65-nm technology node. The extent to which current production capabilities in mask writing, lithography, wafer processing, inspection and metrology can be used is discussed using the results from a 65-nm test chip. The project was a collaborative effort amongst a number of companies in the IC fabrication supply chain. Applied Materials fabricated the 65-nm X Architecture test chip at its Maydan Technology Center and leveraged the technology of other X Initiative members. Cadence Design Systems provided the test structure design and chip validation tools, Dai Nippon Printing produced the masks and Canon’s imaging system was employed for the photolithography.

Narain D. Arora

Papers

Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

Modeling and Characterization of High Frequency Effects in ULSI Interconnects

On-Chip Inductance in X Architecture Enabled Design

Impact of Polysilicon Depletion Effect on Circuit Performance for 0.35μ CMOS Technology

Taking the X Architecture to the 65-nm technology node