Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20I%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A new method to determine ultra-thin gate oxide thicknesses of advanced CMOS devices from C-V characteristics is proposed. The method is based on numerical solutions of the Poisson equation including a first order correction for quantum mechanical effects. Unlike the commonly used C-V methods, this new approach results in a unique value of the gate oxide thickness independent of bias. An efficient and accurate gate oxide thickness determination that is suitable for automatic test procedures is achieved. >

Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects

An experimental technique for accurately determining both the inversion charge and the channel mobility mu of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V/sub DS/ over a wide range of voltages (V/sub DS/=20-100 mV). The resulting mu (V/sub GS/) curves for different V/sub DS/ show no drastic mobility roll-off at V/sub GS/ near V/sub TH/. This suggests that the roll-off seen in the mobility data extracted using the split C-V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering. >

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for determining the minority carrier diffusion length in the base region of Si p‐n junction diodes and solar cells is described. The procedure is to operate the device in the photoconductive mode and to measure its photoresponse in the wavelength region near the energy gap. The ratio of incident light intensity to photocurrent is a linear function of reciprocal absorption coefficient for each wavelength; the slope of the set of points directly yields the diffusion length. In addition, a nonlinear least‐squares analysis is also used to determine the diffusion length.

Diffusion length determination in p‐n junction diodes and solar cells

Degradation of NMOS and enhancement of PMOS I-V characteristics are found to be dependent on specific isolation processes in thin-film SOI devices. These variations are due to mobility decrease in NMOS and increase in PMOS, which can be attributed to the isolation-process-related compressive strain of the silicon film. Magnitudes of mobility variation as high as 40% are observed in the affected SOI devices.

Isolation process dependence of channel mobility in thin-film SOI devices

A novel polysilicon depletion model for MOSFET devices is presented. It is shown that only simple modifications to standard analytical MOSFET models used for circuit simulations are required to account for the polysilicon depletion effect. The accuracy of the model is validated by comparing results to both simulated and measured device characteristics. It is also shown that neglecting the polysilicon depletion effect for devices with nondegenerate polysilicon gates may lead to nonphysical model parameter values and large errors in the calculated intrinsic device capacitances. >

Narain D. Arora

Papers

Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects

A new technique for measuring MOSFET inversion layer mobility

Diffusion length determination in p‐n junction diodes and solar cells

Isolation process dependence of channel mobility in thin-film SOI devices

An analytic polysilicon depletion effect model for MOSFETs