This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2 Gb/s data rate with BER < 10-12 across 14 cm of PCB, and also an 8.0 Gb/s data rate through 4 cm of PCB. Designed in a 1.2 V, 90 nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6 GHz. The total area of each receiver is 0.0174 mm2, resulting in a measured power efficiency of 0.6 mW/Gb/s.

A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS

This paper investigates the fundamental sensitivity of oscillator-based reactance sensors, which are widely used in numerous types of biomedical sensing applications. We first show that the intrinsic sensitivity is limited by the $1/{ f}^{3}$ phase noise of the sensing oscillators. To achieve sensor detection sensitivity below this limit, a correlated double counting (CDC) noise suppression scheme is proposed to cancel the correlated $1/{ f}^{3}$ phase noise in differential frequency detections. The suppression effect of the CDC scheme is thoroughly modeled. Moreover, the CDC scheme is extended to a high-order configuration, called the Interleaving-N CDC, to further improve the frequency resolution. In addition, we show that the weighting sequence on the Interleaving-N CDC data can be optimized as a digital noise filter to maximize the noise suppression. Given a sensing oscillator with any phase-noise profile, a general weighting optimization method is proposed based on the minimum variance distortion less response. As an example, an oscillator-based inductive magnetic sensor array in a 45-nm CMOS silicon-on-insulator process is implemented with the proposed CDC scheme. It achieves a noise suppression of 10.4 dB with basic CDC sheme and a frequency resolution of 0.128 parts per million for Interleaving-N CDC scheme, both with negligible power overhead. This enables inductance-change detection sensitivity of 0.41 fH for a low- $Q$ on-chip 1.6-nH inductor with a quality factor of only 4.95.

Phase Noise and Fundamental Sensitivity of Oscillator-Based Reactance Sensors

This paper presents a distributed multi-phase oscillator based on left-handed LC-ring. In contrast to traditional designs that couple multiple LC-tanks through MOSFETs, it uses an LC-ring as a single high-order resonator that generates multi-phase resonant signal. By avoiding coupling MOSFETs which deteriorate phase noise significantly, it can synthesize multiple phases while maintaining the same phase-noise figure-of-merit (FoM) as a single-stage LC oscillator. This also provides a systematic way of trading power for phase noise. The dynamics and the phase noise of the LC-ring oscillator are analyzed based on a mode-decomposition model. We also address the duality of left-/right-handed resonator in the context of oscillator in detail. These analysis was verified by prototypes in a 0.13 μm CMOS process with 0.5 V supply voltage: a four-stage LC-ring oscillator at 5.12 GHz draws 8 mA current and achieves a phase noise of -121.6 dBc/Hz@600 kHz, while a single-stage one at 5.34 GHz draws 2 mA and achieves -116.1 dBc/Hz@600 kHz. There is a good agreement among analysis, simulation, and measurement.

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A Low-Phase-Noise Multi-Phase Oscillator Based on Left-Handed LC-Ring

This paper presents a 4-path LO generation system with automatic phase tuning for 60 GHz phased-array receivers. Each path employs a linear phase-shift generation chain composed of an injection-locked-oscillator-based phase shifter cascaded with an injection-locked frequency tripler. The frequency tripler with a proposed locking-range enhancement technique is employed to relax both the frequency and the phase shift of the phase shifter for high linearity and low power. Finally, a novel successive-approximation algorithm is proposed to perform automatic phase detection and tuning. Fabricated in a 65 nm CMOS process and occupying a core area of 1.4 ×2.0 mm2, the proposed 4-path LO generation system measures linear phase shift range larger than ±90°, amplitude variation within ±0.4 dB, phase resolution of 22.5°, and maximum phase errors of 22.0° and 1.5° before and after automatic phase calibration while drawing a current of 85 mA from a 1-V supply.

A 4-Path 42.8-to-49.5 GHz LO Generation With Automatic Phase Tuning for 60 GHz Phased-Array Receivers

A 50-Mb/s quadrature phase-shift keying (QPSK)/offset quadrature phase-shift keying (O-QPSK) transmitter suitable for biomedical high-quality imaging application is presented. Centered at 915 MHz, the phase modulation is achieved by directly modifying the self-resonant frequency of an LC voltage-controlled oscillator through capacitor bank switching. By eliminating many unnecessary building blocks in the conventional QPSK/O-QPSK transmitter, significant power and area savings are achieved. Implemented in 0.18- μm CMOS technology, it occupies an active core area of 0.28 mm2. With 305-MHz injection frequency and consuming 5.6 mW under 1.4-V supply, the transmitter achieves error vector magnitude (EVM) of 11.4%/5.97% for O-QPSK/QPSK modulation while delivering output power of -3 dBm at 50 Mb/s. By lowering the injection frequency to 101.67 MHz, it consumes 5.88 mW under the same supply voltages while delivering an output power of -3.3 dBm. The transmitter achieves measured EVM of 6.4% at 50 Mb/s under QPSK modulation.

A 50-Mb/s CMOS QPSK/O-QPSK Transmitter Employing Injection Locking for Direct Modulation

An analytical framework has been developed to describe the transient behavior of negative resistance injection-locked oscillators based on Adler's equation. Design insights are provided by using a combination of analytical simplifications and graphical interpretation. It has been shown that injection locking can be used to meet the requirements for fast hopping systems like the MBOA-UWB specification. The theoretical analysis and design solutions have been verified by extensive simulations on real CMOS processes.

Understanding the Transient Behavior of Injection Locked LC Oscillators

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μm SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

Frequency-Hopped Quadrature Frequency Synthesizer in 0.13- $\mu$ m Technology

This paper presents a fast-hopping frequency synthesizer architecture with quadrature outputs, based on sub-harmonic injection-locking, that is compliant with Wireless-USB/WiMedia specifications. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection locked to a sub-harmonic frequency. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. The overall architecture is a CMOS-only implementation and has been fabricated in 0.13-μm SiGe BiCMOS process. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of −114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

Phased arrays have long been used by the military for radar applications, but have only been recently applied to consumer applications. In a phased array system, one or more narrow beams are generated by transmitting (or receiving) a common RF signal that is phase shifted at the output of each antenna in the array such that the direction of the beams can be varied by controlling the phase difference between consecutive antennas. Microwave transceivers for phased-array radar applications have traditionally been fabricated in III–V technologies like GaAs and InP due to their superior ƒ T and ƒ max . However, modern-day CMOS and BiCMOS technology nodes are now exhibiting ƒ T and ƒ max in the range of 200 to 250GHz, tipping the scales in favor of silicon due to its higher integration capability, lower costs and the availability of significant digital signal processing. Recent designs in CMOS have shown its capability to handle millimeter-wave frequencies [1–3].

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS

We present a novel injection locking frequency generation scheme for UWB systems. In the MBOA-UWB specification, the critical constraint on the frequency synthesizer is the band switching time (< 9.5 ns). In this paper we derive analytical expressions for the transient behavior of injection locked oscillators (ILO) and describe the design constraints on frequency settling of ILOs. We show that they are capable of UWB compliant fast frequency hopping. ILO based frequency synthesizers have a number of advantages over traditional fast hopping LO generation techniques. In particular, it eliminates the need for multiple PLLs and single-sideband (SSB) mixers reducing power consumption and eliminating parasitic spurs.

Narasimha Lanka

Papers

Understanding the Transient Behavior of Injection Locked LC Oscillators

Frequency-Hopped Quadrature Frequency Synthesizer in 0.13- $\mu$ m Technology

A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS

Fast Hopping Injection Locked Frequency Generation for UWB