This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to V dd . It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 ㎒. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

/pdf/two-phase-clocked-adiabatic-static-cmos-logic-and-its-logic-62ey6ymsuz.pdf

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-flipflop are 77.2% and 55.5% less than that in a static CMOS at transition frequencies of 10–100 MHz respectively.

/pdf/two-phase-clocked-adiabatic-static-cmos-logic-2s3necgjx5.pdf

Two phase clocked adiabatic static CMOS logic

This paper presents the simulation results of a 4×4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 µm standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4×4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

https://www1.gifu-u.ac.jp/~yasut/pdf/vlsisoc_paper2010.pdf

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

This paper proposes a Adder circuit based on energy efficient two-phase clocked adiabatic logic. a simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and thence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic in 10 to 200MHz transition frequency range.

Energy Efficient Adiabatic Logic for Low Power VLSI Applications

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.

/pdf/dfal-diode-free-adiabatic-logic-circuits-182u2ebf7r.pdf

DFAL: Diode-Free Adiabatic Logic Circuits

This paper presents a new quasi adiabatic logic family that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. By removing the diode at the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. We design and simulate NOT, NAND, NOR and Exclusive-OR logic gates based on 2PASCL with SPICE implemented using 0.18 ㎛ CMOS technology. A driving pulse with the height equal to V dd is supplied to the gates. From the simulation results, 2PASCL inverter logic can save up to 97% of energy dissipation compared with static CMOS logic at transition frequencies of 10 to 100 ㎒. It also shows the lowest in energy dissipation compared with other proposed simple adiabatic logic inverters.

/pdf/adiabatic-logic-versus-cmos-for-low-power-applications-d9iehdwv0k.pdf

Adiabatic Logic versus CMOS for Low Power Applications

This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 µm CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. From the simulation results, we find that 2PASCL inverter logic can save up to 97% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 10 to 100 MHz. Further, the power dissipation is the lowest when compared with other proposed simple adiabatic logic inverters. 2PASCL also achieves the highest fan-out performance. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

/pdf/fundamental-logics-based-on-two-phase-clocked-adiabatic-156puvpkz5.pdf

Nazrul Anuar

Papers

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

Two phase clocked adiabatic static CMOS logic

Adiabatic Logic versus CMOS for Low Power Applications

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

Fundamental logics based on two phase clocked adiabatic static CMOS logic