High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

Secure and energy-efficient framework using Internet of Medical Things for e-healthcare.

In the Internet of Things (IoT), a wireless sensor network (WSN) is deployed for collecting the interesting data of an application field. Sensor nodes in an IoT WSN are usually with the heterogeneous property. Some nodes have more power (energy) and additional functionality (e.g., data aggregation) than others. Cluster-based routing is usually used in WSNs for data transmissions due to efficiently routing consideration. Based on cluster-based routing, the cluster heads (CHs) act as the sensed data forwarding role. Once one or more CHs fail, the faulty CHs cannot forward the sensed data of their serving sensor nodes. As a result, the sink node (gateway) has not sufficient sensed data of the IoT application field. This will deeply affect the information processing of the IoT applications. We utilize the virtual CH formation and flow graph modeling to efficiently tolerate the failures of CHs. First, the available resources of all failure-free CHs are logically organized as a virtual CH to be the common backup of all faulty CHs. Then, the flow graph modeling is used to achieve fault tolerance with the minimum total energy consumption among all failure-free CHs. Finally, we perform extensive experiments to demonstrate the effectiveness of our approach in the fault-tolerant routing of the IoT WSNs.

/pdf/efficient-fault-tolerant-routing-in-iot-wireless-sensor-20owlo4r2g.pdf

Efficient Fault-Tolerant Routing in IoT Wireless Sensor Networks Based on Bipartite-Flow Graph Modeling

In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both $0~\rightarrow ~1$ and $1~\rightarrow ~0$ single node upsets, with the increased read/write access time.

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Due to the advancement of information and communication technologies, the use of Internet of Things (IoT) devices has increased exponentially. In the development of IoT, wireless sensor networks (WSNs) perform a vital part and comprises of low-cost smart devices for information gathering. However, such smart devices have constraints in terms of computation, processing, memory and energy resources. Along with such constraints, one of the fundamental challenges for WSN is to achieve reliability with the security of transmitted data in a vulnerable environment against malicious nodes. This paper aims to develop an energy-efficient and secure routing protocol (ESR) for intrusion avoidance in IoT based on WSN to increase the network period and data trustworthiness. Firstly, the proposed protocol creates different energy-efficient clusters based on the intrinsic qualities of nodes. Secondly, based on the (k,n) threshold-based Shamir secret sharing scheme, the reliability and security of the sensory information among the base station (BS) and cluster head are achieved. The proposed security scheme presents a light-weight solution to cope with intrusions generated by malicious nodes. The experimental results using the network simulator (NS-2) demonstrate that the proposed routing protocol achieved improvement in terms of network lifetime as 37%, average end-to-end delay as 24%, packet delivery ratio as 30%, average communication cost as 29%, network overhead as 28% and the frequency of route re-discoveries as 38% when compared with the existing work under dynamic network topologies.

https://www.mdpi.com/1996-1073/12/21/4174/pdf

An Energy-Efficient and Secure Routing Protocol for Intrusion Avoidance in IoT-Based WSN

Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is based on the fact that dimension-ordered routing algorithms imposes the highest traffic load on the central nodes in mesh topologies. To balance the traffic over the network, certain routers at the east and the west of NoC, with dimension-order XY routing, statically are configured as YX. Various configurations have been explored for LAXY and the simulations show a specific configuration, called Fishtail , increases mean time to failure of the routers and interconnects by about 42% and 56%, respectively. Moreover, by balancing the load over the network, LAXY improves overall packet latency by about 7% in average, with negligible area overhead.

LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip

Wireless Sensor Networks (WSNs) are prone to faults due to battery depletion of nodes. A node failure can disturb routing as it plays a key role in transferring sensed data to the end users. This paper presents a Fault-Tolerant and Energy-Aware Mechanism (FTEAM), which prolongs the lifetime of WSNs. This mechanism can be applied to cluster-based WSN protocols. The main idea behind the FTEAM is to identify overlapped nodes and configure the most powerful ones to the sleep mode to save their energy for the purpose of replacing a failed Cluster Head (CH) with them. FTEAM not only provides fault tolerant sensor nodes, but also tackles the problem of emerging dead area in the network. Our experimental results and simulations show that FTEAM outperforms conventional protocols in terms of network lifetime and energy consumption. In addition, an analytical evaluation using the Markov model is performed to determine the reliability of the FTEAM.

A fault-tolerant and energy-aware mechanism for cluster-based routing algorithm of WSNs

Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale technologies. BTI gradually increases the absolute value of threshold voltage ( $V_{\mathrm{ th}}$ ) of MOS transistors. The main consequence of $V_{\mathrm{ th}}$ shift of the SRAM cell transistors is the static noise margin (SNM) degradation. The SNM degradation of SRAM cells results in bit-flip occurrences due to transient faults and should be monitored accurately. This paper proposes a sensor called write current-based BTI sensor (WCBS) to assess the BTI-aging state of SRAM cells. The WCBS measures BTI-induced SNM degradation of SRAM cells by monitoring the maximum write current shifts due to BTI. The observations show that the maximum current consumption during write operation is an effective identifier to measure $V_{\mathrm{ th}}$ and SNM shifts. The granularity of BTI assessment of one cell up to a row of memory can be achieved by writing special bit patterns on the memory block during the test. We evaluated the sensor through SPICE-level simulations in 32-nm technology size. The precision of WCBS is about ±1.25 mV (±3.2% error). One sensor is enough for the entire SRAM memory block with negligible area/power overhead; less than 1%. The effects of process variation and temperature changes on WCBS are investigated in detail.

A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories

Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales. The main impact of BTI on SRAM memory cells is the degradation of the static noise margin (SNM), which leads to a higher susceptibility to failures. A variety of techniques for mitigating the impact of BTI on caches have been proposed at architecture level. However, their considerable overheads limit the application of such techniques. Recent studies showed that the utilization of the cache capacity widely varies from one workload to another and even within a workload. When cache utilization is low, for the majority of the cells, the same value is stored for a very long period, which significantly degrades SNM due to BTI. In this paper, we propose a technique to dynamically adjust the cache size according to the running workload cache requirement by monitoring the cache miss rate. The unused cache capacity is power gated to increase the energy efficiency and mitigate aging of the entire cache. The experimental results show that the proposed technique reduces hold and read SNM degradation by up to 48.1% and 33.3%, respectively, at the cost of 2.0% performance penalty.

Bias Temperature Instability Mitigation via Adaptive Cache Size Management

Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about $2.7 \times $ of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging sensors. Furthermore, the presented sensor can detect and correct half of the single event upsets (SEUs), which lead to a bit-flip in the flip-flop. In addition, by utilizing the SEU detection circuitry, a scheme for reducing bias temperature instability, the most important aging process in the memory structures, is presented by balancing the duty cycle of the flip-flop transistors with negligible extra overhead.

Nezam Rohbani

Papers

LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip

A fault-tolerant and energy-aware mechanism for cluster-based routing algorithm of WSNs

A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories

Bias Temperature Instability Mitigation via Adaptive Cache Size Management

A Low-Overhead Integrated Aging and SEU Sensor