Showing papers by "Nitin Chandrachoodan published in 2020"

EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA

Abstract: Neural networks (NNs) have been widely used in many machine learning algorithms and have been deployed for various industrial applications like image classification, speech recognition, and automated control. Spiking neural network (SNN), known as the third-generation neural network, incorporates timing information in the network and is more biologically plausible [1]. Compared to today's artificial and convolutional neural networks (ANN and CNN) where all neurons in each layer will always be activated and computed, SNN only activates those neurons whose membrane potential exceed the threshold potential [2]. As a result, SNN requires fewer computation resources and less data communication between network layers due to its event-driven nature. Although SNN has been blamed for the relatively lower accuracy, recent studies on converted SNNs have improved its accuracy to a similar level of ANN and CNN for smaller network models like MNIST and CIFAR-10, and have demonstrated the great potential of SNN in future deep learning systems [2].

Probabilistic spike propagation for FPGA implementation of spiking neural networks.

Abstract: Evaluation of spiking neural networks requires fetching a large number of synaptic weights to update postsynaptic neurons. This limits parallelism and becomes a bottleneck for hardware. We present an approach for spike propagation based on a probabilistic interpretation of weights, thus reducing memory accesses and updates. We study the effects of introducing randomness into the spike processing, and show on benchmark networks that this can be done with minimal impact on the recognition accuracy. We present an architecture and the trade-offs in accuracy on fully connected and convolutional networks for the MNIST and CIFAR10 datasets on the Xilinx Zynq platform.

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips

Abstract: Microfluidics is an upcoming field of science that is going to be used widely in many safety-critical applications including healthcare, medical research and defence. Hence, technologies for fault testing and fault diagnosis of these chips are of extreme importance. In this study, the authors propose a scalable pseudo-exhaustive testing and diagnosis methodology for flow-based microfluidic biochips. The proposed approach employs a divide-and-conquer based technique wherein, large architectures are split into smaller sub-architectures and each of these are tested and diagnosed independently.

Optimization of DSP Applications Using Parameterized Error Models for Low Power Approximate Adders

Abstract: Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we derive parameterized error models that can be used within any optimization framework in order to optimize the number of approximate bits. We also show that in order to accurately compute the mean square error, the optimization framework needs to take into account not just the functionality of the adder, but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. We demonstrate a significant improvement of accuracy in the prediction of the noise power of DSP systems containing approximate adders.

Depending on HTTP/2 for Privacy? Good Luck!

Abstract: HTTP/2 introduced multi-threaded server operation for performance improvement over HTTP/1.1. Recent works have discovered that multi-threaded operation results in multiplexed object transmission, that can also have an unanticipated positive effect on TLS/SSL privacy. In fact, these works go on to design privacy schemes that rely heavily on multiplexing to obfuscate the sizes of the objects based on which the attackers inferred sensitive information. Orthogonal to these works, we examine if the privacy offered by such schemes work in practice. In this work, we show that it is possible for a network adversary with modest capabilities to completely break the privacy offered by the schemes that leverage HTTP/2 multiplexing. Our adversary works based on the following intuition: restricting only one HTTP/2 object to be in the server queue at any point of time will eliminate multiplexing of that object and any privacy benefit thereof. In our scheme, we begin by studying if (1) packet delays, (2) network jitter, (3) bandwidth limitation, and (4) targeted packet drops have an impact on the number of HTTP/2 objects processed by the server at an instant of time. Based on these insights, we design our adversary that forces the server to serialize object transmissions, thereby completing the attack. Our adversary was able to break the privacy of a real-world HTTP/2 website 90% of the time, the code for which will be released. To the best of our knowledge, this is the first privacy attack on HTTP/2.

Energy Reduction in Turbo Decoding through Dynamically Varying Bit-Widths

Abstract: We investigate the impact of dynamically changing the numerical bit-width across iterations in a BCJR component decoder of a turbo decoder. We show that by performing initial iterations with a larger number of bits but thereafter reducing the number of bits, it is possible to have minimal impact on decoding accuracy. At the same time, this reduction in bit-width can be exploited through appropriate hardware changes to consume less power in the later iterations. We propose a new state encoding mechanism as well as an organization of memory blocks that enables this power reduction, and quantify the effects. When combined with other schemes for early termination, the overall energy consumed per decoding operation can be reduced by between 10–20%.