International Journal of Computer and Applications

‡We describe the use of singular value decomposition in transforming genome-wide expression data from genes 3 arrays space to reduced diagonalized ‘‘eigengenes’’ 3 ‘‘eigenarrays’’ space, where the eigengenes (or eigenarrays) are unique orthonormal superpositions of the genes (or arrays). Normalizing the data by filtering out the eigengenes (and eigenarrays) that are inferred to represent noise or experimental artifacts enables meaningful comparison of the expression of different genes across different arrays in different experiments. Sorting the data according to the eigengenes and eigenarrays gives a global picture of the dynamics of gene expression, in which individual genes and arrays appear to be classified into groups of similar regulation and function, or similar cellular state and biological phenotype, respectively. After normalization and sorting, the significant eigengenes and eigenarrays can be associated with observed genome-wide effects of regulators, or with measured samples, in which these regulators are overactive or underactive, respectively.

Singular Value Decomposition for Genome-Wide Expression Data Processing and Modeling

Preparing the books to read every day is enjoyable for many people. However, there are still many people who also don't like reading. This is a problem. But, when you can support others to start reading, it will be better. One of the books that can be recommended for new readers is computer aided analysis of electronic circuits algorithms and computational techniques. This book is not kind of difficult book to read. It can be read and understand by the new readers.

Computer-aided analysis of electronic circuits: Algorithms and computational techniques

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Enhancing Blockchain security in cloud computing with IoT environment using ECIES and cryptography hash algorithm

Intrusion detection is a problem of great significance to protecting information systems security. An intruder may move between multiple nodes in the network to conceal the origin of attack. Distributed intrusion detection and prevention plays an increasingly important role in securing computer networks. To overcome the limitations of conventional intrusion detection systems, alerts are made in distributed intrusion detection system which are exchanged and correlated in a cooperative fashion. It is necessary to develop fast machine learning based intrusion detection algorithms with high detection rates and low false alarm rates, due to the variety of network behaviors and the rapid development of attack fashions. The system has to observe to trigger thousands of alerts per day, in which most are mistakenly triggered by the false identification. So it is difficult for the analyst to correctly identify alerts related to the attack. This paper presents an intelligent learning approach using Ant Colony Optimization (ACO) based distributed intrusion detection system to detect intrusions in the distributed network. The experimental results on the proposed system with the feature extraction algorithm is effective to detect the unseen intrusion attacks with high detection rate and recognize normal network traffic with low false alarm rate.

ACO based Distributed Intrusion Detection System

Security in wireless ad-hoc networks is a complex issue. The wireless and dynamic nature of ad-hoc networks makes them more vulnerable to security attacks when compared with fixed networks. The existing routing protocols are optimized to perform the routing process without considering the security problem.. Black hole attack is one of the routing attacks in which, a malicious node uses the routing protocol to advertise itself as having the shortest path to the node whose packets it wants to intercept. In this paper we propose a certificate based authentication mechanism to counter the effect of black hole attack. Nodes authenticate each other by issuing certificates to neighboring nodes and generating public key without the need of any online centralized authority. The proposed scheme is implemented in two phases: certification phase and authentication phase following the route establishment process of On Demand Multicast Routing Protocol (ODMRP). The effectiveness of our mechanism is illustrated by simulations conducted using network simulator ns-2.

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Black Hole Attack Prevention in Multicast Routing Protocols for Mobile Ad hoc networks using Certificate Chaining

In JPEG2000 block coding, all coding passes are generated before rate allocation is performed among code blocks. Unwanted passes are then discarded. For low bit-rate coding, this results in a large number of coding passes being discarded. A rate-distortion estimation method that enables precompression rate-distortion optimisation to be carried out, wherein only the required passes need to be coded is presented. Experiments using the proposed technique demonstrate speed-up factors ranging from 1.17 to 1.78 at 0.0625 bpp, for JPEG2000 compression.

Rate-distortion estimation for fast JPEG2000 compression at low bit-rates

Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this paper, we present a methodology to map data-parallel tasks onto hardware that supports partial reconfiguration. The aim is to obtain the maximum possible speedup, for a given reconfiguration time, bus speed, and computation speed. The proposed approach involves using multiple, identical but independent processing units in the reconfigurable hardware. Under nonzero reconfiguration overhead, we show that there exists an upper limit on the number of processing units that can be employed beyond which further reduction in execution time is not possible. We obtain solutions for the minimum processing time, the corresponding load distribution, and schedule for data transfer. To demonstrate the applicability of the analysis, we present the following: 1) various plots showing the variation of processing time with different parameters; 2) hardware simulations for two examples, viz., 1-D discrete wavelet transform and finite impulse response filter, targeted to Xilinx field-programmable gate arrays (FPGAs); and 3) experimental results for a hardware prototype implemented on a FPGA board

/pdf/mapping-data-parallel-tasks-onto-partially-reconfigurable-g5v8lt302z.pdf

Vinita Vasudevan

Papers

Enhancing Blockchain security in cloud computing with IoT environment using ECIES and cryptography hash algorithm

ACO based Distributed Intrusion Detection System

Black Hole Attack Prevention in Multicast Routing Protocols for Mobile Ad hoc networks using Certificate Chaining

Rate-distortion estimation for fast JPEG2000 compression at low bit-rates

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures