Increasing data rates, spectrum efficiency, and energy efficiency have been driving major advances in the design and hardware integration of RF communication networks. In order to meet the data rate and efficiency metrics, fifth-generation (5G) networks have emerged as a follow-on to 4G and projected to have $100\times $ higher wireless date rates and $100\times $ lower latency than those with current 4G networks. Major challenges arise in the packaging of radio frequency front-end modules because of the stringent low signal-loss requirements in the millimeter-wave frequency bands, and precision-impedance designs with smaller footprints and thickness. Heterogeneous integration in 3-D ultrathin packages with higher component densities and performance than with the existing 2-D packages is needed to realize such 5G systems. This article reviews the key building blocks of 5G systems and the underlying advances in packaging technologies to realize them.

A Review of 5G Front-End Systems Package Integration

Chip-embedded mm-wave antenna-integrated modules are demonstrated, for the first time, on panel-scale ultra-thin glass substrates, for high-speed 5G communication standards in the n257 band (26.5 – 29.5 GHz) defined by 3GPP. Co-packaging of amplifiers, filters, and antennas with minimal package parasitics is the key to realize mm-wave package systems. Parasitics arise from on-package and chip-to-package interconnects. This paper focuses on reduced chip-to-package losses and implementation of filters and antennas with chip-embedding structures in glass substrates. To demonstrate the benefits of glass-panel embedding (GPE) for 5G communications, the interconnect losses are benchmarked with the C4-bump based flip-chip technique. The electrical performance shows that the chip-embedding structure with a glass substrate lead to 3X lower insertion loss from chip to antenna than the flip-chip assembly method with C4 bumps. This reduced chip-to-antenna insertion loss brings about the enhanced efficiency and gain of the patch antennas integrated on top of the glass substrates. The process development and electrical performance are benchmarked with emerging 5G substrate technologies such as fan-out wafer level packaging.

Glass-Based IC-Embedded Antenna-Integrated Packages for 28-GHz High-Speed Data Communications

This article presents, for the first time, low-loss small microvias in build-up layers for the next-generation high-density high-performance fifth-generation (5G) millimeter-wave (mm-wave) antenna-integrated packages. As the operating frequency increases, the signal losses in antenna packages become more critical and need to be mitigated to obtain desired performance in beamforming and massive multi-input multi-output. As electrical wavelengths in mm-wave spectra are short, the signal losses caused by microvias dominate the loss budget. To minimize the signal losses and identify the required microvia diameter in build-up layers, this article first focuses on the modeling of small microvias for impedance matching. Based on the models and simulated characteristic impedance, test vehicles with daisy chains are fabricated in build-up layers on a core package substrate. Ultraviolet (UV) laser is utilized to drill microvias, and targeted microvia diameters are obtained through a semiadditive patterning process. High-frequency measurements are also performed to correlate with the models and simulated results in the 28-GHz band. The characterization results exhibit good model-to-hardware correlation and indicate that small microvias (20 $\mu \text{m}$ ) provide impedance closer to $50~\Omega $ compared with the larger microvias. This matched microvia impedance lowers reflection and insertion loss, resulting in a 10% reduction in the signal losses caused by microvias in the 5G New-Radio n257 band around 28 GHz.

Low-Loss Impedance-Matched Sub-25-μm Vias in 3-D Millimeter-Wave Packages

Development of crack-less and deformation-resistant electroplated Ni/electroless Ni/Pt/Ag metallization layers for Ag-sintered joint during a harsh thermal shock

An Ag–Au joint developed by Ag paste joining on electroless nickel/electroless palladium/immersion gold (ENEPIG)-plated direct-bonded aluminum (DBA) substrate was employed in SiC (Silicon carbide) power modules. The ENEPIG plating was modified to possess high mechanical strength by thickening the Ni layer to 20 μm. The reliability of SiC/DBA die-attached module by Ag–Au joining was evaluated during a long-term thermal shock test (TST) from − 50 to 250 °C up to 2000 cycles. The shear strength of as-sintered Ag–Au joint was evaluated to be 37.6 MPa, but it showed a significant decrease after 1000 thermal cycles and maintained stably from 1000 cycles to 2000 cycles. Based on the microstructural evolution via EBSD observation, it was confirmed, by modifying ENEPIG, the Ag–Au interfacial deformation derived from Al plastic deformation was successfully suppressed even after 2000 cycles. In this case, the mechanism for shear strength degradation was found to be the interfacial delamination between Ag paste layer and ENEPIG substrate. This can be ascribed to the large thermal stress caused by different coefficients of thermal expansion (CTE) of power module components. This study not only realized the deformation-free structure for Ag–Au joint during long-term thermal cycling but also provided fundamental insights for fracture behaviors of Ag–Au sinter joint.

Modified Ni/Pd/Au-finished DBA substrate for deformation-resistant Ag–Au joint during long-term thermal shock test

Fifth-generation (5G) communications have been driving major package innovations to enable low-loss interconnects between the integrated circuits (IC) and other system components such as antenna arrays. Antenna-in-package with three-dimensional (3D) or double-side component is widely pursued as the front-up architecture to realize this vision. The interconnect height and losses are critical parameters in these 3D package structures. Copper sintering paste is emerging as an ideal candidate to replace solders for both off-chip and on-package interconnects because of the resulting higher electrical conductivity and relatively simple manufacturability with additive processes. This article focuses on computational modeling, optimization of sintering conditions, and electrical conductivity measurements of highly conductive copper paste to verify the proposed model. The model is based on two-particle sintering theory, which describes the neck growth evolution of copper paste at the initial stage of sintering. The neck-growth model shows good consistency with the measured neck size of copper, and hence can be used to provide guidelines for the sintering conditions of copper paste. The celectrical conductivity measurements suggest that the copper paste sintered at 260°C for 30 min shows a electrical conductivity of 1.4 × 107 S/m, which is 82% higher than that of solder. In addition, this article investigates the potential of copper paste interconnect technology in high-frequency applications such as in 5G millimeter-wave communications. The transmission lines patterned with the copper paste show good correlation with simulated results in the millimeter-wave frequency band. The high-frequency characterization also indicates that the copper paste enables simple circuit patterning, offering equivalent signal losses with plated copper. The detailed analyses discussed in this article suggest the eligibility for multi-applications of copper sintering paste in IC packaging.

Sintered Nanocopper Paste for High-Performance 3D Heterogeneous Package Integration

High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4x10^7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.

Low-Loss Additively-Deposited Ultra-Short Copper-Paste Interconnections in 3D Antenna-Integrated Packages for 5G and IoT Applications

With the number of connected-devices increasing tremendously, communication data rates are projected to be at least 10–100X in the 5G/mm-wave (MMW) technology - much higher than the existi...

Nobuo Ogura

Papers

Sintered Nanocopper Paste for High-Performance 3D Heterogeneous Package Integration

Low-Loss Additively-Deposited Ultra-Short Copper-Paste Interconnections in 3D Antenna-Integrated Packages for 5G and IoT Applications

First Demonstration of Ultra-Thin Glass Panel Embedded (GPE) Package with Sheet Type Epoxy Molding Compound for 5G/mm-wave Applications