Localization is one of the key technologies in wireless sensor networks (WSNs), since it provides fundamental support for many location-aware protocols and applications. Constraints on cost and power consumption make it infeasible to equip each sensor node in the network with a global position system (GPS) unit, especially for large-scale WSNs. A promising method to localize unknown nodes is to use mobile anchor nodes (MANs), which are equipped with GPS units moving among unknown nodes and periodically broadcasting their current locations to help nearby unknown nodes with localization. A considerable body of research has addressed the mobile anchor node assisted localization (MANAL) problem. However, to the best of our knowledge, no updated surveys on MAAL reflecting recent advances in the field have been presented in the past few years. This survey presents a review of the most successful MANAL algorithms, focusing on the achievements made in the past decade, and aims to become a starting point for researchers who are initiating their endeavors in MANAL research field. In addition, we seek to present a comprehensive review of the recent breakthroughs in the field, providing links to the most interesting and successful advances in this research field.

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A Survey on Mobile Anchor Node Assisted Localization in Wireless Sensor Networks

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control phys ...

/pdf/integrating-mems-and-ics-3tx6wanytd.pdf

Integrating MEMS and ICs

Through-Silicon Vias (TSVs) have garnered a lot of interest in recent years because TSV is a key enabling technology for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP). There has been significant effort in TSV fabrication and electrical design. However, considerably less work has been done on thermo-mechanical analysis and mechanical design of these structures. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the conducting material in the vias, thermo-mechanical reliability is a major concern. This paper uses Finite-Element (FE) models and X-ray diffraction (XRD) experiments for the thermo-mechanical analysis of TSVs. Two-dimensional thermo-mechanical Finite-element models have been built to analyze the stress/strain distribution in the TSV structures, and the models show that large stress gradients and plastic deformation exist near the corner of electroplated Cu pads. The stress results from the finite-element models have been compared against XRD experimental data. A fracture mechanics analysis has also been performed, and the fracture analysis shows that Cu/SiO 2 interfacial cracks and SiO 2 cohesive cracks are more likely to initiate and propagate at those corner locations.

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Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the More-Than-Moore paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

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Power module packaging technologies have been experiencing extensive changes as the novel silicon carbide (SiC) power devices with superior performance become commercially available. This article presents an overview of power module packaging technologies in this transition, with an emphasis on the challenges that current standard packaging face, requirements that future power module packaging needs to fulfill, and recent advances on packaging technologies. The standard power module structure, which is a widely used current practice to package SiC devices, is reviewed, and the reasons why novel packaging technologies should be developed are described in this article. The packaging challenges associated with high-speed switching, thermal management, high-temperature operation, and high-voltage isolation are explained in detail. Recent advances on technologies, which try to address the limitations of standard packaging, both in packaging elements and package structure are summarized. The trend toward novel soft-switching power converters gave rise to problems regarding package designs of unconventional module configuration. Potential applications areas, such as aerospace applications, introduce low-temperature challenges to SiC packaging. Key issues in these emerging areas are highlighted.

A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues

Improved aluminum-gallium-nitride (Al
 x
Ga
 1-x
N) p-i-n photodetectors with different active regions are reported, designed for the measurement of UV-A (315 to 380 nm), UV-B (280 to 315 nm), and UV-C (<; 280 nm) radiation. The spectral responsivity of Al
 x
Ga
 1-x
N photodetectors can be tailored by bandgap engineering of the Al
 x
Ga
 1-x
N layers and integration of filter layers. Intrinsically visible-blind p-i-n photodetectors are measured on-wafer and packaged in TO-18 headers. Photocurrent measurements in photovoltaic mode result in responsivity values of up to 0.21 A/W for UV-A (EQE = 70%), 0.14 A/W for UV-B (EQE = 56%), and 0.11 A/W for UV-C (EQE = 57%), respectively. The room temperature dark current density values as low as 30 pA/cm
 2
 at a reverse bias of -3 V yield a specific detectivity of more than 4 × 10
 14
 cm Hz
 0.5
/W. Response time data of the p-i-n photodiodes indicate a rise time of 1.7 ns and a fall time (1/e) of 4.5 ns. Long-term stability tests over 1000 h at an irradiance of 5 W/cm
 2
 demonstrate the potential of these photodetectors for demanding applications such as the continuous monitoring of high irradiance ultraviolet light sources.

Improved AlGaN p-i-n Photodetectors for Monitoring of Ultraviolet Radiation

“System-in-Package” is a key concept to achieve minimum size and costs in hybrid integration. We investigated several related technologies for inertial sensor MEMS packaging, with special emphasis on vacuum packaging of resonant devices like gyroscopes: Hermetic Chip-to-Wafer and Wafer-to-Wafer bonding, Through-Silicon Via in thick and in thin wafers, thin-film getter deposition and fine patterning, and full-wafer transfer molding. This paper shows the achievements of the project after finalizing the main R&D activities. Currently, we are attempting the full flow implementation on functional devices.

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Investigation of key technologies for System-in-Package integration of inertial MEMS

Power electronics has gained an enormous significance in the European research area: With CO2 reduction as one of the grand challenges in our industrial society, the economy asks for large-scale energy harvesting from natural regenerative resources on one hand, and for energy efficient electronic devices on the other. Although power electronics systems have their own challenges, there is a general trend towards miniaturization that is almost comparable to the history of microelectronics. Key technologies like wafer thinning and assembly operations like die attach and thick wire or ribbon bonding are on their way to a considerable market. Embedded in a regional north-German competence cluster, the Fraunhofer-Institute for Silicon Technology ISIT investigates novel technologies for power electronics module integration. In this paper, we want to present our latest progress in large Copper ribbon bonding. Our work was performed on test diodes and DBC substrates, using 200 μm thick and 2 mm wide Copper ribbons.

Copper ribbon bonding for power electronics applications

The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.

Norman Marenco

Papers

Improved AlGaN p-i-n Photodetectors for Monitoring of Ultraviolet Radiation

Investigation of key technologies for System-in-Package integration of inertial MEMS

Copper ribbon bonding for power electronics applications

TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

Copper ribbon bonding for power electronics applications