Showing papers by "Nuno Lourenço published in 2022"

Low-Cost, Deep-Sea Imaging and Analysis Tools for Deep-Sea Exploration: A Collaborative Design Study

Abstract: A minuscule fraction of the deep sea has been scientifically explored and characterized due to several constraints, including expense, inefficiency, exclusion, and the resulting inequitable access to tools and resources around the world. To meet the demand for understanding the largest biosphere on our planet, we must accelerate the pace and broaden the scope of exploration by adding low-cost, scalable tools to the traditional suite of research assets. Exploration strategies should increasingly employ collaborative, inclusive, and innovative research methods to promote inclusion, accessibility, and equity to ocean discovery globally. Here, we present an important step toward this new paradigm: a collaborative design study on technical capacity needs for equitable deep-sea exploration. The study focuses on opportunities and challenges related to low-cost, scalable tools for deep-sea data collection and artificial intelligence-driven data analysis. It was conducted in partnership with twenty marine professionals worldwide, covering a broad representation of geography, demographics, and domain knowledge within the ocean space. The results of the study include a set of technical requirements for low-cost deep-sea imaging and sensing systems and automated image and data analysis systems. As a result of the study, a camera system called Maka Niu was prototyped and is being field-tested by thirteen interviewees and an online AI-driven video analysis platform is in development. We also identified six categories of open design and implementation questions highlighting participant concerns and potential trade-offs that have not yet been addressed within the scope of the current projects but are identified as important considerations for future work. Finally, we offer recommendations for collaborative design projects related to the deep sea and outline our future work in this space.

Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models

Abstract: The design of integrated circuits (ICs) in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices on the circuits’ layout, a task that has stubbornly defied all automation attempts. In this paper, disruptive research using modern embedding techniques and a fully unsupervised attention-based encoder - decoder model is conducted to automate the placement task of analog IC layout design. The attention-based graph-to-sequence model, AGraph2Seq for short, differs from other heterogeneous graph embedding approaches by introducing structure in both the input and output data in an encoder - decoder architecture. The structure allows for a smaller and more effective placement regression model, drastically reducing the number of trainable parameters and turning the model inherently independent of the circuit topology in terms of the way devices are connected and the number of devices in a circuit, turning it easily scalable to circuits with higher complexity. Additionally, the attention mechanism makes the model’s decoder invariant to the input devices’ order. The deep model is ultimately trained in an end-to-end fashion to minimize a fully unsupervised loss function that efficiently evaluates the fulfillment of fundamental placement’s topological constraints. As a proof of concept, the final model, but also its intermediate stages, i.e., encoder -only, decoder -only, and encoder - decoder without attention, are extensively used to propose different placement solutions for several modern analog IC blocks in multiple deep nanometer technology nodes at push-button speed, including topologies not present in the training set. These present a level of generalization beyond traditional analog IC placement methodologies and most recent machine learning-based approaches and compete with or outperform highly optimized analog layouts and human-made designs.

Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling

Abstract: This work presents a study of two analog front-end circuit architectures for heartbeat detection. Both circuits present an amplification block as the first stage, followed by a band-pass filter. In the first, the heartbeat detection is done using an adaptive threshold based on pulse-width, whereas the heartbeat detection in the second is done using a sample and hold to find the maximum and minimum peak of each beating. Both architectures are modeled in Verilog-A and simulated using real-world ECG signals with different characteristics. This work studies possible fundamental analog circuit blocks suitable for wearable implementation. It evaluates critical performances requirements from the analysis of the behavior simulations. It was verified that the first circuit can properly detect heartbeats as long as the input-referred noise is below 21 μV, whereas the second one ensures it until 30 μV. The low cutoff frequency can be approximately 10 Hz without compromising the signal’s peaks, which means that these specifications can be relaxed substantially compared to systems intended to reconstruct the signal accurately.

Machine Learning Approaches for Transformer Modeling

Abstract: In this paper, several machine learning modeling methodologies are applied to accurately and efficiently model transformers, which are still a bottleneck in millimeter-wave circuit design. In order to compare the models, a statistical validation is performed against electromagnetic simulations using hundreds of passive structures. The presented models using machine learning techniques have proven to be accurate, efficient, and useful for a wide range of frequencies from (around) DC up to the millimeter-wave range (around 100GHz). As an application example, the models are used as a performance evaluator in a synthesis procedure to optimize a transformer and a balun.

ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage

Abstract: Deep learning (DL) models are now a reality towards the automation of the placement task of analog integrated circuit (IC) layout design, promising to bypass the limitations of existing approaches. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, and symmetry island (SI) constraints are described, and an unsupervised loss function is used for the artificial neural network (ANN) model to learn how to generate placements that follow them. As only sizing data is required for its training, it discards the need to acquire legacy layouts containing insights of these types of constraints. The model is ultimately used to produce floorplans from scratch, at push-button speed, for state-of-the-art analog structures, including technology nodes not used for its training.

Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors

Abstract: Automatic simulation-based sizing approaches are essential in designing radio-frequency (RF) integrated circuit (IC) blocks for modern applications. However, optimizations considering process, voltage, and temperature (PVT) corners or layout still pose unprecedented challenges in applying these tools due to the high simulation times and different simulator convergence issues. This paper proposes two different deep learning (DL) models to assist the PVT-inclusive simulation-based sizing process of RF ICs, and more specifically, voltage-controlled oscillators (VCOs). Given specific devices’ dimensions, the 1st model classifies the likeability of the circuit to convergence for nominal and PVT corners, bypassing solutions that will hardly produce valuable information for the optimization process, while the 2nd model predicts the VCOs’ oscillating frequencies for the aforementioned conditions. The methodology is tested on a state-of-the-art VCO, reducing 19% of the workload of the circuit simulator, ultimately saving almost 5 days of computational effort and with improvement on the optimization result.

Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient

Abstract: This paper describes a radiation-hardened bandgap voltage reference (BGR) for space applications. The BGR has a second-order curvature compensation and can deliver a stable output voltage and current for N-type and P-type loads through internal resistors or, optionally, through an external precision resistor. The circuit includes three 8-bit trimming resistive ladders for post-fabrication calibration of the temperature compensation slope, output voltage, and output current value. The circuit is designed for reliable performance in space application, considering process, voltage, and temperature variations and the impact of single-event transients and total ionizing dose. The BGR was designed in a 180 nm silicon-on-insulator CMOS technology, using radiation-hardened devices to provide a 1.25 V reference voltage and a 20 μA current reference, and occupies a 920×430 μm2 area. After trimming, the nominal post-layout simulation over the temperature range of −40 to 125°C shows the BGR achieving a 2.7 ppm/°C temperature coefficient, 6.13 ppm/°C in the worst case.

Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization

Abstract: Analog IC design is characterized by non-systematic re-design iterations, often requiring partial or complete layout re-design. The layout task usually starts with device placement, where the several performance figures and constraints to be met escalate its complexity immensely, and, due to the inherent tradeoffs, an “optimal” floorplan solution does not usually exist. Deep learning models are now establishing for the automation of the placement task of analog integrated circuit layout design, promising to bypass the limitations of existing approaches based on: time-consuming optimization processes with several constraints; or placement retargeting from legacy designs/templates, which rely heavily on legacy layout data. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover the different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, proximity, and symmetry island constraints are formulated for the first time in the literature, and an unsupervised loss function is used for the artificial neural network model to learn how to generate placements that follow them. The use of a deep learning model makes push-button speed placement generation possible, additionally, as only sizing data are required for its training, it discards the need to acquire legacy layouts containing insights into this vast set of, often neglected, constraints. The model is ultimately used to produce floorplans from scratch at push-button speed for real state-of-the-art analog structures, including technology nodes not used for training. A case-study comparison with a floorplan design made by a human-expert presents improvements in the fulfillment of every constraint, reaching an overall improvement of around 70%, demonstrating the approach’s value in placement design.

A Radiation-Hardened Frequency–Locked Loop On–Chip Oscillator with 33.6ppm/°C Stability for Space Applications

Abstract: This work presents a 16MHz on_chip oscillator based on a frequency_locked loop (FLL) which is radiation hardened by design and intended for space applications. The oscillator maintains a high temperature stability over a wide range oftemperatures, process and voltage variations. The FLL presents a 7-stage current starved ring oscillator using output signal combiners for lower radiation sensitivity. Furthermore, the system presents high reconfigurability by using several DACs to adjust the oscillator’s output frequency and the temperature slope dependency. This reconfigurability is especially useful to maintain all performances across PVT variations.

Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs

Abstract: The automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks in deep nanometer technologies has moved towards process, voltage, and temperature (PVT)-inclusive optimizations, to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations’ capabilities to their limits. This paper presents innovative research towards the automation of RF IC design by using deep learning to assist the simulation-based sizing tools in time-consuming PVT-inclusive optimizations. The proposed PVT regressor inputs the circuit’s sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. The proposed controlled PVT estimator is tested on a state-of-the-art class C/D voltage-controlled oscillator, reducing the workload of the circuit simulator up to 79% while achieving a speed-up factor of $2.92 \times $, ultimately saving more than 16 days of computational effort.

Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS

Abstract: Low-noise amplifiers (LNAs) play a significant role in modern millimeter-wave (mmWave) integrated circuit multi-standard transceiver systems. This paper proposes a transformer-less LNA based on a cascade of two AC coupled common source stages, each with inductive degeneration, for the 28-GHz 5G communications band. An automatic design methodology explores the topology design space over a 148-dimensional performance space spreading through different corners for process, voltage, and temperature. It results in about 1000 optimized LNA variants, with gains achieving up to 17.5-dB, and the noise Figure and power consumption down to 2.4-dB and 1.86-mW, respectively. These performance figures position the adopted LNA’s performance boundaries with the most recent mmWave LNAs.

Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation

Abstract: The layout design of analog integrated circuits has been defying all automation attempts, and it is still primarily a handcrafting process carried by circuit designers on traditional layout editing frameworks. This paper presents a toolbox based on deep learning techniques and a sturdy graphical user interface to assist designers during that process. The underlying mechanism of this toolbox relies on a simple pairwise device interaction circuit description, i.e., the circuits’ topological constraints, to propose valid floorplan solutions for block-level structures, including topologies and deep nanometer technology nodes not used for its training, at push-button speed. Despite its automatic functionalities, the toolbox is focused on explainable artificial intelligence, involving the designer in the synthesis flow via filtering and editing options over the candidate floorplan solutions. This constant state of human-machine feedback environment turns the designer aware of the impact of each device’s position change and inherent tradeoffs while suggesting subsequent moves, ultimately increasing the designers’ productivity in this time-consuming and iterative task. Finally, the toolbox is shown to instantly generate floorplans with similar or better constraint fulfilment than human designed solutions for state-of-the-art analog circuit blocks.