ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented The history and evolution of SCR device used for on-chip ESD protection is introduced Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products

/pdf/overview-of-on-chip-electrostatic-discharge-protection-4ap3vu5ogb.pdf

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed. >

ESD: a pervasive reliability concern for IC technologies

Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.

Nano-cmos circuit and physical design

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V/sub DD/ and V/sub SS/ are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects. >

Internal chip ESD phenomena beyond the protection circuit

V/sub DD/-V/sub SS/ protection design considerations to meet MIL-STD requirements are discussed. Internal chip electrostatic-discharge (ESD) damage due to direct stress applied between V/sub DD/ and V/sub SS/ pins is illustrated, and possible solutions are discussed. It is shown that induced current paths can exist when outputs/inputs are stressed with respect to V/sub DD/ or V/sub SS/ stress, and if the internal layout is not carefully considered, the overall protection level can degrade. An unusual internal ESD phenomenon that was observed for I/O pins stressed with respect to V/sub DD/ is reported. The results show that there exists a window of threshold voltages where the I/O protection is not effective due to interaction with the internal chip layout. >

O. Adams

Papers

Internal chip ESD phenomena beyond the protection circuit

Internal chip ESD phenomena beyond the protection circuit